Overview | Schedule | Exhibitor List

DesignCon99: Five Top Conferences, One Outstanding Learning Experience

At DesignCon99, you'll attend seminars, technical forums, keynote presentations, and plenary sessions led by top design engineers, who will present their information in a practical, straightforward fashion, without the marketing hype you see at other events.

If you want the facts, and nothing but the facts, DesignCon99 is the event for you.

Regardless of your background, job function, or product interest, DesignCon99 has something for you. Five outstanding technological conferences cover every aspect of design engineering, from system-driven integrated circuit design and wireless communications technologies to HDL design methodologies and intellectual property issues.

DesignCon99 is the only event designed just for practicing design engineers. At DesignCon99, case studies and design solutions will be presented—and demonstrated—by practicing engineers to assist you in your current design projects and programs.

In short, DesignCon99 offers serious and practical information to design engineers who are serious about their work.

If you're looking for an event where you will

• Discover solutions to your most pressing design challenges
• Learn more about the industry's latest strategies and technological advances
• See those strategies and technologies at work through live product demonstrations
• Trade notes with your peers from the design engineering community
• Gain knowledge you won't find anywhere else

You need to attend DesignCon99!

Who Attends DesignCon?
Virtually everyone and anyone who needs to keep up to date on design engineering theory, technique and application strategies. DesignCon attracts engineers and allied professionals from all levels and disciplines, including:

• Advisory Engineers
• Chief Scientists
• Circuit Designers
• CMOS Circuit Analysis and Development Engineers
• Company Presidents
• Design Engineers
• Directors of Research and Development
• EDA Engineering Managers
• Embedded System Designers
• Engineering Fellows
• Engineering Managers
• Field Applications Engineers
• Hardware Engineers
• Hardware Verification Engineers
• Hardware/Software Engineers
• IC Design Engineers
• Investment Analysts
• Members of Technical Staffs
• Principal Design Engineers
• Principal Engineers
• Program Directors
• Project Engineers
• Project Leaders
• Project Managers
• Research and Development Engineers
• Senior Engineers
• Senior Members of Technical Staff
• Senior Productivity Engineers
• Signal Integrity Engineers
• Software Engineers
• Staff Research Engineers
• System Design Engineers
• System Engineering Managers
• System-on-Chip Design Managers
• Team Leaders
• Technical Vice Presidents
• Venture Capital Analysts
• Vice Presidents of Engineering
• Vice Presidents of Research and Development

On-Chip System Design Conference
Learn more about the most critical issues and leading-edge techniques in system-driven integrated circuit design at the On-Chip System Design Conference. Among the highlights of this conference are "system view" IC design methods and new validation approaches necessary for deep sub-micron designs.

Specific sessions to be presented in this conference include the following:

• Codesign of IP in On-Chip System Applications
• Design Techniques that Boost Processing Speed in CPU Designs
• An Object-Oriented Simulator-Independent Environment for Logic Verification of Systems-on-a-Chip
• Behavioral Synthesis: Ready for Primetime
• On-Chip Decoupling Capacitor Design and Modeling Methodology
• A Virtual Prototype System for PDA Software Development
• Integrated Software, Hardware, and Verification for Programmable ASIC Systems
• The Effects of Signal Integrity in Sub-Micron Chip Design
• Formal Verification of the Hewlett-Packard V-Class Servers
• Designing ICs for the Next Generation
• Achieving Timing Convergence between Synthesis and Place and Route
• Debugging Aids for Systems-on-a-Chip
• Design for PowerPC G4 Microprocessor
• Electrical Interconnect Guideline Development for Noise Avoidance in a High-Performance Microprocessor
• Unique MP Verification Techniques for Symmetric Multiprocessing Systems
• On-Chip System Core Integration Techniques
• A Case Study: The Timing Driven Layout of Four Ultra Pad Limited Deep Sub-Micron ASICs
• A New Approach to Chip-Level Thermal Analysis
• Noise Management in Large Scale Mixed Signal Devices
• 4kV ESD Protection for Mixed Voltage IOs in a 400 MHz Microprocessor
• A BIST Methodology for Standard Cell Designs Using Hierarchical Layout Techniques
• Silicon Validation of Capacitance Models in a Full-Chip Parasitic Extractor
• Using White-Box Techniques for Deep Functional Verification
• Timing Impact Minimization of JTAG Designs
• A Semicustom Circuit Library Methodology for System-on-Chip Designs

High-Performance System Design Conference
Methods designed to obtain the highest possible performance from general-purpose and embedded digital systems are the focus of the High-Performance System Design Conference. Areas to be addressed by this conference include backplane signal integrity techniques, signal integrity and timing issues, and system simulation.

Specific sessions to be presented in this conference include the following:

• Signal Integrity Characteristics of Printed Circuit Board Parameters
• A Tour of the IBIS Accuracy Specification
• Accurate Models for Signal Integrity Analysis
• Bus LVDS (BLVD) Technology in Heavily Loaded Backplanes
• Pentium II GTL+ Interface Design
• Designing Redundant Clock Trees with PLL Clock Drivers
• Controlling Clock Uncertainty in High Speed System Designs
• Taking Advantage of Delay—Correlation Effects to Design High Speed Digital Circuits
• Measuring and Analyzing PCI Performance in Real Applications
• The Voodoo and Black Magic Associated with High Performance Backplane Designs
• Improve Signal Integrity of IEEE 1394: Physical Layer with Time Domain Reflectometry
• Decoupling Capacitor Techniques for High-Frequency Board Designs
• The Role of Capacitors in High-Speed System Design
• Designing Three-Point AGP Solutions Using Simulation Techniques
• Using Both VHDL and Verilog for Board-Level Simulation
• Probes and Setup for Measuring Power-Plane Impedances with Vector Network Analyzer
• Introducing IEEE 1149.1: Boundary Scan into the Board-Level Development Process
• Design-Oriented Analysis of Power Bus for High-Speed Systems
• A Sound Strategy for Managing the Performance of High-Speed ULSI Packaging
• Design for Debug
• PCB Impedance Design, Beyond the IPC Recommendations
• Compact PCI at 66 MHz
• The Impact of PWB Construction on High-Speed Signals
• Using I₂O in Embedded PCI Systems

Digital Communications System Design Conference
Digital communication is where the worlds of telecommunications and computers collide. The Digital Communications System Design Conference focuses on the technologies and tools that enable these disciplines to come together to provide the network services demanded by today's end users.

Specific sessions to be presented in this conference include the following:

• Addressing Cost, Performance, and TTM Objectives Simultaneously
• Advances in Dense Wavelength Division Multiplexing
• Design and Implementation Issues of Soft IP for All-Digital Broadband Modems
• Kalman Filtering for Enhanced Global-Positioning Accuracy
• High-Performance Backplane Application with the Texas Instruments GTL+
• Network Management in Switched Gigabit Environments: Part of the Hardware Infrastructure
• Implementing Gigabit Ethernet over Copper Now
• Fibre Channel Tutorial
• Arrayed Optics—The Next Paradigm Shift—A Roadmap to Terabit Class Equipment
• Time-Triggered Protocol-Fault-Tolerant Serial Communications for Real-Time Embedded Systems
• IS-54 Digital Cellular Modem Design
• System Verification: Essential for Digital Wireless System-on-a-Chip Designs
• Creating a Switched Network Architecture for Gigabit Ethernet: The Need for a New Switching Paradigm
• Next Generation Networks: Chasing Bandwidth with GTL+
• Hardware Split Radix FFT Designed Using C2Verilog Compiler
• Modeling and Simulation of a Mixed DSP/RF Transmitter in a Coded OFDM WLAN Application
• Wireless Local Loop from a Switching Point of View
• Operating at 1 Gbps Over HIPPI-6400
• OC-48/2.5 Gbps Interconnect Engineering Design Rules
• HDSL2: Designed to Operate with Mixed Services
• Versatile Embedded Controllers for Thin Client Applications
• Optimizing Network Performance in Standard High-Volume Servers
• Home Networking Using Existing Residential Phone Wiring
• Reuse of Configurable Stacked Protocol Utilities for Verification of Datacom ASICs

New! The Intellectual Property (IP) World Forum
Intellectual property—the incorporation in software of the intellectual components of an integrated circuit—presents a number of business and technological challenges to the design engineering industry. These challenges are the focus of the IP World Forum, the newest addition to DesignCon.

Specific sessions to be presented in this conference include the following:

• The Move from ASIC Design Flow to Customer-Owned Tooling: A DVD/MPEG-2 System-on-a-Chip Case Study
• System-on-a-Chip Design and Verification
• High-Performance Reconfigurable Signal Processor with Adaptive VLIW Architecture
• ASIC Core Verification with Emulation
• Design and Application of a Configurable On-Chip Bus and Bus Controller
• Tips and Techniques for Creating Synthesizable, Reusable High-Level Building Blocks in VHDL
• Solving Design Issues for a 1394 Camera
• Code Translation of a Reusable Soft IP
• Configuration Management: It's Not Just for Software Anymore
• Novel Design Techniques for the Design of an Embedded Microprocessor Core
• Creating and Deploying Design Methodology Framework
• Hard IP Migration and Reuse
• ASIC Rapid Prototyping through Design Reuse and Software Models
• Protecting Your Virtual Components: A Model and Technqiues
• A Comparison of USB and 1394 Video Camera Designs
• Verification Code Reuse
• Anatomy of a Protected Model
• IP-Based Architecture Exploitation
• Rapid Prototyping to Verify Complex Systems-On-Chip
• When Does It Make Sense to Design for Reuse?
• IP-Based Architecture Synthesis
• Building a Legally Sound Intellectual Property Portfolio
• Design of a Dynamically Configurable Content-Addressable Memory
• Intellectual Property Business Models: Who Will Be the Microsoft of the EDA Industry—And the Next Bill Gates?

The Programmable Logic Design Conference

PLDCon focuses on design methodologies, technologies, and solutions that utilize programmable logic. The conference highlights advancements in PLD design and applications, including those involving memory control, processor interfaces, and multimedia.

Specific sessions to be presented in this conference include the following:

• An Embedded Processor Core Stethoscope
• Selecting a Graphical HDL Entry Tool
• Boosting Design Productivity with High-Performance, High-Density Programmable ASICs
• FIFO Applications Enabled by Embedded RAM in FPGAs
• Self-Diagnosis and Repair: An Essential Capability for Systems-on-Chip with Embedded DRAM
• Advantages of Designing with Low-Voltage Programmable Logic Devices
• Retargeting FPGAs: A PCI Card Design Example
• Abstraction and Modeling in VHDL Functional Simulation
• A Designer's Guide to CPLDs and FPGAs
• Method and Implementation of Intelligent Peripherals
• Embedded 66 MHz PCI Functions on an FPGA