DesignCon 2006

DesignCon 2006

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Management Forum Panel

Tuesday, February 7

2:00 pm - 3:15 pm

Managing Verification ROI: Assessing the Business Impact of Bug Escapes

Technical Panel

Wednesday, February 8

3:45 pm - 5:00 pm

Why Do So Many Chips Fail? A Panel Discussion on Design Verification

TecForums

Tuesday, February 7

8:30 am - 9:10 am

6-TA1
Designing of Printed Circuits Using Substrates with Combined Embeddion

Monday, February 6

1:30 pm - 4:30 pm

TF-MP1
Beyond RTL: Advanced Digital System Design

Thursday, February 9

9:00 am - noon

TF-THA1
Getting Started with SystemVerilog Assertions

Technical Papers

Monday, February 6

8:30 am - 9:10 am

3-TA1
Why Is My Customer a Better Verification Engineer than Me?

9:20 am - 10:00 am

3-TA2
Automated Risk Elimination by Formally Critiquing Verification Plan and Design Documentation

4-TA2
Phase Locked Loop Design for Mobile WiMAX Radio

10:15 am - 10:55 am

3-TA3
Functional Verification of a Multi-Gigabit Transceiver IP in an FPGA

11:05 am - 11:45 am

3-TA4
A Multiparadigm Verification Flow

2:00 pm - 2:40 pm

3-TP1
Leveraging Assertions in SystemVerilog Testbench to Get to Closure

2:50 pm - 3:30 pm

3-TP2
Verification Planning to Functional Closure of Processor-Based SoCs

Wednesday, February 8

8:45 am - 9:25 am

3-WA1
Verifying the TriCore2 Multithreaded Microprocessor

9:40 am - 10:20 am

3-WA2
The ABV Capability Maturity Model

2:50 pm - 3:30 pm

3-WP2
Nexus-Based Multicore Debug