Poseidon provides "processor-based" design analysis, optimization and acceleration tools for Platform, SOC and FPGA designers. Poseidon's tools enable the designer to perform architectural analysis and HW/SW partitioning in a SystemC environment. DSP algorithms can be easily mapped from ANSI C to a hardware accelerator and efficient RTL is generated. Increase performance, lower cost and reduce time to market with Triton tool suite, supports ARM, PowerPC and Nios architectures, and is optimized for audio, video, VoIP, imaging, wireless, and security applications.

Poseidon Triton tool suite is comprised of two tools, Tuner and Builder, which provides the designer with tools to fully develop an efficient processor-based architecture. Poseidon's Tuner tool offers hardware and software architects an easy to use SystemC simulation environment to quickly analyze and optimize complex systems. With the Builder Tool, time critical algorithms can be easily partitioned from software to hardware and an efficient hardware accelerator generated, Significant increases in performance and/or power reductions can be achieved. With Triton tools designers can tradeoff performance, power and cost. These tools support ARM, PowerPC, MicroBlaze and Nios II architectures on ASIC, FPGA and structured array platforms. The solutions are optimized for video, VoIP, audio, imaging, wireless, networking, and security devices.