Lightspeed has developed and patented technology to build Mask Reconfigurable Intellectual Property including Logic Arrays built out of Standard Cells -enabling low cost ASSP product family extension and customization, Platform ASICs, or Structured ASICs; Multi-function I/Os -enabling Platform ASICs with the ability to change I/O standards using only a single metal layer; and embedded test -AutoTest ® and SiliconView ® for Structured ASIC families.

Lightspeed's Logic Array technology is the industry's leading array-based logic solution for deep sub-micron semiconductor design, supporting logic requirements in ASSPs, CSSPs, Platform ASICs, and Structured ASICs. Standard cell based - these logic arrays deliver the highest performance and highest density.

Typical Usage Models:
ASSP—™® replaces traditional standard cell for a portion or all of the logic in the chip CSSP facilitates customer-specific IP regions on the device, reducing required volume for economic viability, and speeding time-to-silicon Platform ASIC allows companies to create multi-use silicon platforms, speeding time-to-market and lowering cost, while reducing engineering expense and lowering COGS.

Lightspeed's Mask Reconfigurable I/O supports a wide range of signaling standards in a single I/O slot using a single PHY. The I/O standard can be selected with a single metal mask. MultiFunction I/O provides high flexibility and high performance for use with mask reconfigurable logic technology embedded in a SoC or for creating a Structured ASIC.

Lightspeed's test technology enables Platform ASICs or Structured ASICs where the test burden can be completely eliminated from the design team. AutoTest 99.5% stuck-at fault coverage - no user test vectors SiliconView In-circuit access to all chip state via JTAG pins