The Collett data clearly shows that the failure rate of first silicon is rising. This appears to be a trend rather than just a one-time problem, so the industry needs to establish what the failure mechanism is and how to fix it. Are the design paradigms that we have used for the past decade breaking down? Do we need to establish new rules for how design is performed? Is it a failure of the verification methodology to catch the problems? Many designers blame management for not deciding on the specification early enough, but those managers claim they are just responding to market forces. Are the system designers not doing a good enough job in defining how parts of the system are meant to interact? This panel will try to work out where a design team should be placing its efforts to ensure success the first time around.

Brian Bailey
Consultant
Brian Bailey Consulting

Brian Bailey is an independent functional verification consultant, helping system designers improve their verification efficiency and providing guidance and technology services to small start-up companies. He has spent more than 20 years creating verification solutions in a number of EDA companies, and in recent years he has spent most of his time helping the industry understand how and when to adopt new verification methodologies. He is active in the standards community, chairing a group within Accellera. He graduated from Brunel University in England in 1981 with a first-class honors degree in electrical and electronic engineering.

Tom Anderson
Director, Technical Marketing
Synopsys, Inc.

Mr. Anderson has more than 20 years experience in hardware design, IP development, and EDA. Prior to Synopsys, he was vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP provider Virtual Chips, and in management positions at several semiconductor and system suppliers. Mr. Anderson is chairman of the Virtual Socket Interface Alliance (VSIA) functional verification working group.

Sergio Camerlo
Director, Engineering, Data Center, Switching, Wireless, Technology Group
Cisco Systems

Mr. Camerlo's current organization is strongly focused on high-speed interconnects and advanced packaging technology and its application to next-generation products. Mr. Camerlo's work on signal, timing, power integrity, and high-speed backplanes layout engineering has been successfully applied to several products currently in production. Mr. Camerlo is also chairing the Cisco Switching Patent Committee and is involved with the industry and academia to foster the development of new high-speed interconnects and packaging materials and methodologies.

Ira Chayut
Verification Manager
nVidia

Mr. Chayut's career has been focused on ASIC functional verification for the past 15 years. Prior to that, he worked on software and systems design, starting at Bell Labs. He has authored ECAD tools for ASIC and PCB design, co-founded a start-up, and was co-inventor of a file server appliance.

Grant Martin
Chief Scientist
Tensilica, Inc.

In addition to his current role at Tensilica, Mr. Martin is currently co-chair of the DAC Technical Program Committee for Methods for 2005 and 2006 and previously co-chaired the VSI Alliance Embedded Systems Study Group in the summer of 2001. Mr. Martin's particular areas of interest include system-level design, IP-based design of SoC, platform-based design, and embedded software. He is also a senior member of the IEEE. Mr. Martin received his bachelor's and master's degrees in mathematics (combinatorics and optimization) from the University of Waterloo, Canada, in 1977 and 1978, respectively.

Kevin Normoyle
Normoyle Engineering

Russ Vreeland
Broadcom