Bryan Lewis
Research Vice President and Chief Analyst
Gartner Dataquest
Mr. Lewis joined Dataquest in 1985 and founded Dataquest's ASIC/SoC/FPGA research. He has responsibility for tracking and evaluating market movements, forecasting markets, and tracking technology trends. He is a key speaker at numerous conferences and consults with a wide range of worldwide clients. Mr. Lewis received a B.S. in marketing from the University of Oregon.
Brett Cline
Vice President, Customer Operations and Services and Corporate Communications
Forte Design Systems
Mr. Cline joined the Forte team in 1999 and served as vice president of marketing from 2002 until 2005, where he drove the product direction and customer introduction of Forte's Cynthesizer, now the industry's leading behavioral synthesis product. He is currently responsible for Forte's consulting and support services, driving key account customer success. Before joining Forte, Mr. Cline was director of marketing at Summit Design, where he managed both the verification product line, including HDL Score, and marketing communications; Mr. Cline joined Summit through their acquisition of Simulation Technologies in 1997. Mr. Cline has also held positions in development, applications, and technical marketing at Cadence Design Systems and General Electric. He holds a B.S. in electrical engineering from Northeastern University in Boston, Massachusetts, and serves as an advisor to several small EDA start-ups.
Kam Kittrell
General Manager, Design Implementation Business Unit
Magma Design Automation
Mr. Kittrell has served as general manager of Magma's Design Implementation business unit since 2005, having held a number of management positions in applications and product engineering since joining Magma as an applications engineer in 1999. Before joining Magma, he served as a product engineer for Ambit Design Systems, continuing in that role after Ambit was acquired by Cadence Design Systems. He has 17 years of experience in ASIC design implementation and holds a bachelor's degree in electrical engineering from Texas A&M University.
Rakesh B. Sethi
Director of Business Development, Custom SoC and Foundry Business Unit
Toshiba America Electronic Components, Inc.
Dr. Sethi is responsible for establishing and implementing marketing and sales strategies for system-level ICs targeted at the consumer and communications market, as well as playing a leadership role in strategic customer alliances in the United States. He began his career with TAEC in 1998 as senior manager of business development. Dr. Sethi was previously president of CShore Microelectronics Corporation. Prior to that, he served as principal technology manager of EEPROM-based PLD/CPLDs at Cypress Semiconductor. Before that, he served as section head of the Non-Volatile Memory group at National Semiconductor Corporation. He earned a Ph.D. in electrical engineering from Lehigh University and attained certification from the Executive MBA Institute at Stanford University.
Ed Wan
Senior Director, Design Services Marketing
TSMC North America
Mr. Wan is responsible for the company's design services strategy and product marketing. Before joining TSMC, Mr. Wan was chief executive officer of Spike Technologies, a leading chip design services company in Milpitas, California. He also served as the vice president of worldwide field engineering at United Microelectronics Corporation, where he directed the internal design activities as well as the external network of library, IP, and design services providers. Mr. Wan also held the position of vice president at Cadence and LSI Logic, where he managed LSI Logic's North American design centers. He started his technology career as a circuit designer, applications engineer, and product engineer at Signetics Corporation. Mr. Wan has a B.S. in electrical engineering from UC Berkeley.
Mobashar Yazdani
ASIC Program Manager
Hewlett Packard
Mr. Yazdani started working at HP in 1988 on its first generation of CMOS RISC processors and on various ASICs for the HP enterprise computer line. He was a member of the HP Labs VLSI group for the development of HP's Wide Word Architecture, and developed the flow for the design of large-size high-performance ASICs and SoCs in HP Labs. Mr. Yazdani was principal scientist in HP procurement for assessment of silicon providers, and managed the ASIC/ASSP technology center in HP supply chain operations for a number of years. Mr. Yazdani is currently in the R&D lab of the HP Product Process organization's ASIC program, supporting ASIC development for HP worldwide. Mr. Yazdani has worked extensively on industry IP standardization. His current interests include new models of ASIC design, development, and IP integration. He holds a B.S. in electrical engineering and an M.S. in electrical engineering from the University of Texas at Austin and the University of Kentucky, respectively.