Suresh Rajgopal
Principal Engineer
STMicroelectronics
Dr. Rajgopal is a principal engineer at the STMicroelectronics Data Storage Division Design Center in San Diego. He has more than 13 years of experience in the industry working in the areas of design automation, low-power design, SoC and CPU architecture, system design, modeling, and verification. His product background spans microprocessors, mobile terminals, networking, on-chip interconnects, and hard disk read channels. He has a Ph.D. in computer science and engineering from the University of North Carolina at Chapel Hill.
Jasbinder Bhoot
Senior Director, IP Applications Marketing
eASIC Corporation
Mr. Bhoot has more than 15 years of ASIC and FPGA experience. Prior to joining eASIC, he was part of the vertical marketing team at Xilinx. In this role, he managed the partner solutions team that included IP, design services, EDA, and ASSPs. Mr. Bhoot has also held technical and business management positions at LSI Logic, Altera, Sony Semiconductor, and Texas Instruments. Mr. Bhoot holds a B.S. in electronic engineering from the University of Westminster and an M.B.A. from the University of Nottingham.
J. Augusto de Oliveira
Vice President and Senior Fellow
Philips Semiconductors
Mr. Augusto de Oliveira is responsible for setting the strategic direction for the Philips Semiconductors' processor, DSP cores, and platform enabler roadmaps. From 1999 to 2005, he was chief architect and innovation manager for the consumer business of Philips Semiconductors, leading the architecture definition and technical strategy for the Nexperia digital video platform and managing the creation of lead products and critical IP for the platform.
Grant Martin
Chief Scientist
Tensilica
In addition to his current role at Tensilica, Mr. Martin is currently co-chair of the DAC Technical Program Committee for Methods for 2005 and 2006 and previously co-chaired the VSI Alliance Embedded Systems Study Group in the summer of 2001. Mr. Martin's particular areas of interest include system-level design, IP-based design of SoC, platform-based design, and embedded software. He is also a senior member of the IEEE. Mr. Martin received his bachelor's and master's degrees in mathematics (combinatorics and optimization) from the University of Waterloo, Canada, in 1977 and 1978, respectively.
Jordan Selburn
Principal Analyst, Core Silicon
iSuppli
Mr. Selburn came to iSuppli with decades of extensive experience in ASIC, programmable logic and semiconductor intellectual property (IP) analysis, product marketing, and engineering development. Prior to joining iSuppli, he served as the director of product marketing for Amphion Semiconductor, where he was responsible for management of the technical product marketing team. He launched products in all of Amphion's product families, in addition to providing in-depth sales support for the products and the IP business model. Prior to his tenure with Amphion, Mr. Selburn was the principal analyst for ASIC and IP at Gartner Group/Dataquest and, as such, was responsible for the evaluation and analysis of semiconductor IP, as well as the ASIC and programmable logic markets. He formulated and presented tracking and forecasting on technology and market trends, with particular emphasis on system-level integration, as part of his duties at Gartner Group/Dataquest. Mr. Selburn holds an M.S. in engineering economic systems from Stanford University, in addition to an M.B.A. with distinction from Santa Clara University, and a B.S. in electrical engineering with honors from the University of Michigan.
Naveed Sherwani
Co-Founder, President, and Chief Executive Officer
Open-Silicon
Dr. Sherwani brings to Open-Silicon more than 19 years of experience in technical engineering and general management. Prior to co-founding Open-Silicon, Dr. Naveed was the founder and general manager of Intel Microelectronics Services. During his nine-year tenure at Intel, Dr. Naveed served in various technical and managerial positions. Dr. Naveed led various efforts to promote the use of ASIC-style methodologies to improve design efficiency and time-to-market. Dr. Naveed was a co-architect of the Intel microprocessor design methodology and environment that has been used in various leading microprocessors. Prior to joining Intel, Dr. Naveed worked as a consultant for various telecommunications and computer companies, mainly focusing on ASIC-style design flow and cell library design to improve time-to-market. He also served as a professor at Western Michigan University, where his research concentrated on VLSI physical design automation, combinatorics, and graph algorithms.