Stuart Sutherland, Lead Engineer, Sutherland HDL, Inc.

The IEEE P1800 SystemVerilog standard includes a powerful assertions language that provides all the power and capabilities needed for verification of today's complex hardware designs. SystemVerilog assertions (SVA) can concisely describe very complex sequences of logic changes and signal relationships. SVA provides all the power and capabilities needed for verification of today's complex hardware designs. This half-day tutorial will give verification engineers and engineering managers an in-depth look at the capabilities of SystemVerilog assertions, and a full understanding of how complex logic sequences are described using SVA.