Design for manufacturing, or DFM, rapidly is becoming a chief business concern for the semiconductor and EDA industries, given the enormous economic impact of designing advanced semiconductor products right the first time. Companies are doing everything they can to optimize performance and power and to build reliable products that are easy to manufacture, in an effort to reduce cost and time to market and ultimately get the best return on their investment. But this quest for reasonable yields and associated profitability-that now involves designers, EDA suppliers, foundries, DFM startups, fabless design houses, and others-is peppered with obstacles, due to technological complexity, such as the switch from 90 nm to 65 nm, and skyrocketing mask costs. Compounding the problem, there are no real guidelines for measuring DFM cost versus ROI. For example, designers would need to follow rules to be measured against yield, and yet that measure does not exist today.

Dennis Wassung, Jr.
Vice President, Equity Research Analyst
Canaccord Adams

Mr. Wassung currently focuses on the Advanced Design & Test Technologies franchise at Canaccord Adams, specifically the EDA, semiconductor test, and mechanical design industries. He joined the firm in 1999 as an associate analyst to concentrate on semiconductor testing, test handling, and interfacing solutions, as well as next-generation test methodologies and strategies. Prior to joining Canaccord Adams (previously Adams Harkness), he spent five years at Teradyne as a mechanical engineer, designing mechanical interfaces for semiconductor test equipment. He earned a B.S. in mechanical engineering from Rensselaer Polytechnic Institute and an M.B.A. in finance from the University of Southern California's Marshall School of Business. He is also a CFA charterholder.

Thomas F. Blaesi
Vice President, Marketing Business Development
SIGMA-C

Mr. Blaesi joined SIGMA-C as vice president of marketing and business development in August 2004 to guide its DFM directions. He has more than 15 years of global strategic-marketing experience in electronic design automation and semiconductors with companies in Europe and Silicon Valley. Mr. Blaesi has held senior marketing positions at two start-ups, Pact XPP Technologies and Silicon Design Systems, and has served as director of business development and director of system-chip design services for Cadence Design Systems. Earlier he also served as group product-marketing manager/physical design for Synopsys. Previously, at LSI Logic, he was product marketing manager/design methodology and tools in Munich, and product marketing manager/ASIC design methodology in Silicon Valley. Mr. Blaesi began his career as an application engineer for Valid Logic Systems of Munich. He holds a degree in electrical engineering from the University of Applied Sciences in Furtwangen, Germany.

Jean-Marie Brunet
Market Development Manager
Mentor Graphics

Mr. Brunet is market development manager for litho-friendly design products at Mentor Graphics. Prior to Mentor, he led the AE and Technical Marketing group at OPC start-up Aprio. Previously, he spent more than 10 years in IC design and design management positions at STMicroelectronics, Cadence Design Services, MUSIC Semiconductors, Micron, and Silicon Design Systems. He has managed engineering teams delivering complex nanometer designs with significant signal-integrity, noise, and yield issues and experienced the challenge of working with pure-play fabs to resolve yield issues related to OPC/RET. Mr. Brunet earned his M.S. in electrical engineering from I.S.E.N Electronic Engineering School in Lille, France.

Riko Radojcic
Design to Silicon Initiative
CDMA Technologies
Qualcomm

Dr. Radojcic is a consultant with 20+ years experience in the semiconductor industry, specializing in process-design integration and design for manufacturability (DFM). He is currently a consultant with Qualcomm CDMA Technologies and several EDA start-up companies. Previously, he served in various managerial and engineering roles at PDF Solutions, Tality, Cadence, Unisys, Burroughs, and Ferranti Electronics, UK. He has published more than 25 papers, co-authored a book, and participated in a number of industry conferences and events. He received his B.S. and Ph.D. degrees from the University of Salford, UK.

Edward Wan
Senior Director, Design Services Marketing
TSMC North America

Mr. Edward Wan is currently the senior director of design services marketing at TSMC North America. Before joining TSMC, Mr. Wan was chief executive officer of Spike Technologies, a leading chip-design services company in Milpitas, California. Prior to Spike Technologies, he was vice president of worldwide field engineering at United Microelectronics Corporation, where he directed the internal design activities as well as the external network of library, IP, and design services providers. Mr. Wan also held the positions of vice president at Cadence and vice president of engineering at LSI Logic, where he managed LSI Logic's North American design centers. He started his technology career as a circuit designer, product engineer, and applications engineer at Signetics Corporation. Mr. Wan has a B.S. in electrical engineering from UC Berkeley.

Jim Wiley
Senior Technical Director
Brion Technologies

Mr. Wiley's responsibilities include product positioning, technical partnerships, and business development. Before joining Brion, he spent nearly 20 years at KLA-Tencor directing reticle defect inspection development strategies based on industry analysis and forecasting of advanced photomask and wafer lithography technologies. Prior to KLA-Tencor, Mr. Wiley was active in the IC mask manufacturing and CAD as founder and vice president of Technology for Master Images, director of engineering for Ultratech, and mask/CAD engineering at National Semiconductor. Mr. Wiley has been an active author and leader in IEEE, SPIE, and BACUS (SPIE's Photomask Technology Group), having served three terms as president of BACUS. A published author on reticle defect printability, Mr. Wiley holds seven patents on mask manufacturing, reticle inspection, and defect printability. He earned his B.S. degree in photographic science from RIT.

Yervant Zorian
Vice President and Chief Scientist
Virage Logic

Dr. Yervant Zorian has served as Virage Logic's vice president and chief scientist since joining the company in 2000. Prior to that, Dr. Zorian served as a distinguished member of the technical staff at Lucent Technologies, Bell Laboratories, and chief technical advisor to LogicVision.

Dr. Zorian also serves as the vice president of the IEEE Computer Society for Conferences and Tutorials and is the editor in chief emeritus of IEEE Design and Test of Computers. He founded and presently chairs the IEEE 1500 standardization working group for embedded core test, and has authored more than 250 papers and four books. Dr. Zorian has received a number of best paper awards, is an honorary doctor of the National Academy of Sciences of Armenia, is a fellow of the IEEE, and is the recipient of the 2005 IEEE Industrial Pioneer Award. Dr. Zorian received an M.S. from the University of Southern California and a Ph.D. from McGill University.