Steven McKinney, Technical Marketing Engineer, Mentor Graphics
Panch Chandrasekaran, Connectivity Marketing Manager, Xilinx, Inc.
Gourgen Oganessyan, Senior Electrical Engineer, Molex
David Brunker, Technical Fellow, Molex
Tim Hemken, Director of Marketing, Xilinx, Inc.
This presentation will introduce high-speed system designers to a novel and broadly applicable technology designed to establish and demonstrate the operating margin of channels in 10+ Gbps serial systems. An interactive hardware and simulation tool will be described that enables rapid comparison of reference channel performance with that of selectively degraded channels. These degraded-performance channels incorporate a full set of critical channel parameters: insertion loss, return loss, and varying levels of crosstalk. The performance of the link will then be assessed under varying channel conditions by monitoring silicon response and then be used to establish a functional operating margin.
Craig Rawlings, Director of Business Development, Kilopass Technology, Inc.
Charles Ng, Business Development Manager, Kilopass Technology, Inc.
Embedded non-volatile memory (eNVM) is an emerging area that enables the integration of non-volatile programmability into the SoC. This is important for applications such as the following:
- Security: Chip ID, security keys, HDMI, DRM
- Yield Enhancement and Quality Improvement: Wafer tracking, LCD drivers and calibration, CMOS image sensors
- Configuration and parameter storage: configurable firmware and hardware in post production
- Digital trim of analog circuits: mixed signal SoC applications
- Code storage: MCU, MPU, DSP, and other embedded micro-components all need resident code storage
Brian Bailey, Consultant, Brian Bailey Consulting
Harry Foster, Chief Methodologist, Jasper Design Automation
Assertions have quickly become accepted as a viable tool in the functional verification portfolio, as they have demonstrated their ability to find tough bugs and have helped to stimulate the emergence of the formal verification market. However, the property languages that power assertions have much more potential that is not yet being exploited in the ESL space today. They hold the promise to be the next generation of design languages providing the ability to define intent rather than a possible implementation of that intent. In this poster, we will look at some of the areas in which property languages could be used today and some of the extensions necessary to allow them to cover a greater percentage of the design problems.
Kazuhiro Yamazaki, Marketing Manager, Oak-Mitsui Technologies
Yoshi Fukawa, President and Chief Executive Officer, TechDream, Inc.
Interest is growing for the use of embedded capacitors due to space savings, improved electrical performance, and reliability. One of the roadblocks to implementation has been the ability to simulate what benefits one would get if one used this technology without having to first build a prototype. This poster will show one way to address this issue. Reduction of chip capacitors on the PWB surface using a power/ground simulation tool was compared with actual potential voltage. We found good correlation of the simulated to actual performance. Furthermore, we observed the effect that thin capacitor substrates have as power/ground planes. The voltages were more stable with greatly reduced resonances. We will show that by using thin core planes and this simulation tool, one can reduce the Posterer of discrete capacitors and get better electrical performance.
Joseph Fjelstad, Founder, SiliconPipe, Inc.
Three dimensional packaging structures have risen significantly in importance over the last few years. Stacked chips, stacked packages and even stacked wafers have been developed or explored for to meet density needs of portable products, high density memory and the like. However, the third dimension also offers significant potential performance benefit when applied to high speed applications. This poster submission will graphically illustrate how significant improvement is system performance can be simply achieved and at reduced power. The submission will show interconnection structures that can be created and provide both measured and modeled data as supporting evidence of the potential.
Mohamed A. Salem, Mentor Graphics
The CE-ATA standard is an optimized interface for SFF storage in consumer electronics. This poster will introduce an overview of the CE-ATA. It will explain the standard's leverage of technologies such as ATA and MMC, as well as the protocol layers that enable a host interface with storage device. It will project the technology in real design cases of host/device controller IP cores. It will also outline the architecture of the CE-ATA cores, as well as solutions for the hardware design challenges. Further, it will pinpoint a primitive "know-how" baseline for the CE-ATA technology supported by design cases of IP cores designed for integration into consumer electronics' SoCs.
Vaishnavi Shankar, Vice President, Business Development, Mirabilis Design, Inc.
Current RTL verification solutions focus solely on implementation correctness. This approach ensures that most input possibilities and corner cases are validated by running bit patterns against the RTL. For complex SoC and custom ASIC designs, this verification strategy is a brute force approach and is still incomplete. It does not verify that the device RTL is tested to work correctly in the system. Correctness metrics are a function of the application software, workload, and traffic and are dependent on the environment. They are not random stimuli. For networked systems and wireless devices, QoS, channel throughput, distortion correction, and end-to-end latency are some functional metrics. These each depend on the interaction with other system elements and the environment. The Specification-to-Verification solution to be presented uses a graphically constructed macro-architecture ESL model initially created to specify system architecture function with performance and uses it to verify the functional correctness of the RTL model. This approach compliments implementation verification and reduces both the verification time (simulation time and time to create the stimuli) and increases product quality.
Jian Xu, Ph.D. Candidate, North Carolina State University
AC-coupled interconnects (ACCI), either capacitively coupled or inductively coupled, have non-contacting structures and use RZ pulses signaling. Researchers at NC State University are exploring the application of ACCI on L1-L3 packaging and intra/inter 3D IC. This poster will present two demonstrations for capacitively coupled chip-to-chip communications on MCM as well as PCB: 1) two flip-chips on MCM communicating 2.5-Gbps PRBS via chip-substrate capacitors over a 5.7cm lossy line, and 2) two bare-chips on PCB communicating 2-Gbps PRBS via on-chip MIM capacitors over a 17cm FR4 trace. This poster will also present a demonstration for inductively coupled vertical signaling in 3D IC: two stacked chips with 90um thickness communicating 2.8-Gbps PRBS via an inter-chip transformer and tolerant 50um misalignment.