Panch Chandrasekaran, Connectivity Marketing Manager, Xilinx
Steve Baker, Senior High-Speed Architect, Mentor Graphics

The exacting technological demands created by increasing bandwidth requirements have given rise to significant advances in FPGA technology that enable engineers to successfully incorporate serial IO interfaces in their designs. This presentation will describe an effective approach for designing and implementing a system with SERDES links that operate in the multi-gigabit range. It includes design techniques to overcome challenges in the various stages of a design of a high-speed serial interface followed by a practical description of how to take advantage of available component technology and design solutions to achieve a working design.