Henry Yu, Principal Engineer, Mentor Graphics
Mandar Chitnis, Development Engineer, Mentor Graphics
Rakesh Jain, Mentor Graphics Corporation
Darren Zacher, Mentor Graphics Corporation

Today's FPGA devices offer dedicated hardware resources such as DSP, whose use is critical when meeting design specifications. At the same time, a desire to keep costs low by using the smallest device possible implies the need to trade off the use of this limited resource effectively. This presentation will describe a framework for managing critical device resources through the synthesis process. Built on an experimental layer that includes a predictive module-generation engine, the presentation guides users through a combination of automated and user-driven capabilities to help them make informed tradeoffs and thus make the most efficient use of resources within the context of the limitations of the device, while meeting design specifications.