Kalyan Thumaty, Vice President & General Manager, X Architecture Cadence Design Systems, Inc.
Narain Arora, Vice President of Technology, Cadence Design Systems.

As VLSI device scaling continues, interconnect delay has emerged as the dominant component of timing calculation. It is this increased interconnect delay that has prompted the replacing of (Al) wires with copper wires, reducing the wire RC delay to almost half. An alternative way to minimize interconnect delay is to re-architect the IC wiring by making pervasive use of diagonal lines, called the X Architecture. The use of diagonal wire to connect two corner points of a square results in 29.3% wire length reduction and one via elimination, compared to orthogonal wiring. Monte Carlo simulations show that X-architecture will result in about 17% wire length reduction. Recently it has been reported that X-architecture enables IC chips to achieve on an average of 20% wire length reduction and 30% fewer vias [2] compared to the same design in Manhattan wiring.