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Schedule

3-TP2
Verification Planning to Functional Closure of Processor-Based SoCs
Tuesday, February 7 | 2:50 pm - 3:30 pm

Andrew Piziali, Cadence Design Systems

In today's fast-paced electronics market, time to first pass, fully functional silicon is the ultimate determinant of financial success. Functional verification typically ends up being the most unbounded problem in the flow. While teams struggle with verification, the root causes of these struggles are the lack of a comprehensive verification plan and automation of the verification process which leverages that plan. This presentation will describe the problem and present an approach to verification planning which leads to a high-quality plan. It will conclude with an example of verification automation, specifically highlighting the connection to an executable verification plan.