Leena Singh, Cadence Design Systems, Inc.
Tim Pylant, Cadence Design Systems, Inc.

This presentation will address some best practices in functional verification by making use of assertions for static or dynamic checking, functional coverage, and SystemVerilog for testbench. It also will address how to construct different components of the verification environment (for example, BFMs, monitors, stimulus generation, etc.) for ease of reuse in multiple projects and platforms. It will illustrate, through a complete verification example, how designers can compose their block-level environment with assertions, coverage, and a testbench that finds more bugs and is also reusable.