Ning Xue, Altera Corp.
Ramanand Venkata, Altera Corporation
Arch Zaliznyak, Altera Corporation
Divya Vijayaraghavan, Altera Corporation
Steve Park, Altera Corporation
Chong Lee, Altera Corporation
Rakesh Patel, Altera Corporation

The process of verifying a configurable IP is more complex and time-consuming than IP design. This presentation will address a "divide-and-conquer" functional verification methodology for a highly configurable multi-gigabit transceiver IP used in a FPGA chip. Topics such as verification methods, reusable testbenches, hardware emulation tests, mixed-signal validation, and test-coverage measurements are covered to show how the IP is efficiently verified for tape-out and later characterized in the lab. The advantages of the presented method include comprehensive test coverage, testbench reusability in chip simulations, hardware emulation and lab bring up, and improved verification efficiency.