Jeff Li, Superior Logic Corporation

There are always risks of missing bugs in functional verification. Using a formal analysis engine with very high capacity, enables one to eliminate such risks by formally proving that it is safe not to run a given class of test cases. This risk elimination solution works well with all verification flows because it only requires the waveform of a transaction and some user interaction (indicating what will be well verified about this transaction) in addition to the Verilog RTL. If it finds any test case in the class that can show any surprise, it generates a Verilog testbench to use in a normal simulation/debugging environment.