Alfonso Iniguez, Verification Engineering, Freescale Semiconductor

Why is it that after months of directed and random testing you were not able to find a bug that your customer found within two days of receiving samples? Is there anything wrong with your testbench? Should you blame it on faulty assertions? Could it be that you did not run your simulation long enough? Could the bug have been discovered by using better functional coverage? The intention of this presentation is to answer all those questions by analyzing past mistakes and proposing an approach to writing a verification plan.