Janick Bergeron, Scientist, Synopsys

The SystemVerilog standard is the result of an industry-wide effort to extend the Verilog language to include enhanced modeling and verification features. The integration of verification features creates a unified language that brings enhanced design and advanced verification technologies, including assertions, together to deliver increased designer productivity and more effective verification. This tutorial will provide an overview of the SystemVerilog Verification Methodology Manual and will show the benefits of unifying the advanced design and verification features of SystemVerilog, using assertions, object-oriented programming, random stimulus, constraint solving and functional coverage.