Ken Willis, Architect, Cadence Design Systems
Joel Martinez, Marketing Manager, Product Marketing, Altera
Mike Resso, Business-Development Manager, Signal-Integrity Applications, Agilent Technologies

This paper will discuss how CAE design tools, FPGAs, and test/measurement equipment all play important roles in a design methodology for multi-gigabit serial links. A new breed of CAE tools will be discussed that support modeling interconnect with s-parameters and allow rapid simulation of millions of data bits such that the worst case effects of inter-symbol interference can be analyzed. In addition, the flexibility and time to market advantages of designing multi-gigabit data channels utilizing FPGAs will be covered. And finally, utilizing test and measurement equipment to validate multi-gigabit transceivers are performing at required data rates will also be discussed.