2005 Archive
Highlights | Schedule | Exhibitor List
Schedule view: By Date | By Track
Monday January 31
9:00am - 12:00pm
TF1: Architecture and CAD Software for FPGAs
TF2: Embed Resistors and Capacitors in Circuit Boards Now
TF3: Multi-gigabit Serial Channel Design Methodology - from Architecture, Through Prototype, to Physical Measurement Verification
TF4: Eliminating Unwanted Test Fixture Effects in Multi-Gigabit Device Measurements: Coupled Line S-Parameter Deembedding and Thru-Reflect-Line (TRL) Calibration Technique
TF5: An Introduction to the Electronic System Level (ESL)
TF6: Recent Developments in Signal Integrity Measurement and Analysis
TF1: Architecture and CAD Software for FPGAs
TF2: Embed Resistors and Capacitors in Circuit Boards Now
TF3: Multi-gigabit Serial Channel Design Methodology - from Architecture, Through Prototype, to Physical Measurement Verification
TF4: Eliminating Unwanted Test Fixture Effects in Multi-Gigabit Device Measurements: Coupled Line S-Parameter Deembedding and Thru-Reflect-Line (TRL) Calibration Technique
TF5: An Introduction to the Electronic System Level (ESL)
TF6: Recent Developments in Signal Integrity Measurement and Analysis
1:30pm - 4:30pm
TF7: Inductance of Bypass Capacitors: How to Define, How to Measure, How to Simulate?
TF8: Customized Synthesis for Structured ASICs - Delivering Higher Performance, Quicker Time to Market and Reduced Work on the Back End
TF9: Implementing a Coverage-Driven Constrained-Random Design-for-Verification Methodology with SystemVerilog
TF10: Nanoelectronics TecForum
TF11: Transition to Surface-Mount: An Analysis of Signal Integrity Improvement vs. Manufacturing Concerns in Multi-Gigabit Systems Using High-Density Connectors
TF12: Signal Integrity Techniques for High Speed Serial Link Design
TF7: Inductance of Bypass Capacitors: How to Define, How to Measure, How to Simulate?
TF8: Customized Synthesis for Structured ASICs - Delivering Higher Performance, Quicker Time to Market and Reduced Work on the Back End
TF9: Implementing a Coverage-Driven Constrained-Random Design-for-Verification Methodology with SystemVerilog
TF10: Nanoelectronics TecForum
TF11: Transition to Surface-Mount: An Analysis of Signal Integrity Improvement vs. Manufacturing Concerns in Multi-Gigabit Systems Using High-Density Connectors
TF12: Signal Integrity Techniques for High Speed Serial Link Design
Thursday February 3
9:00am - 12:00pm
TF13: Discussing the Limitations and Accuracies of Time and Frequency Domain and analysis of Physical Layer Devices
TF14: Advances in Time and Frequency Domain Measurements, Modeling and Signal Integrity Analysis of Gigabit Interconnects
TF15: Volatile Memory Performance Comparison
TF13: Discussing the Limitations and Accuracies of Time and Frequency Domain and analysis of Physical Layer Devices
TF14: Advances in Time and Frequency Domain Measurements, Modeling and Signal Integrity Analysis of Gigabit Interconnects
TF15: Volatile Memory Performance Comparison
Tuesday, February 1
8:30am - 9:10am
1-TA1: Implementing High Speed SPI4.2 Interfaces Using FPGAs
1-TA1: Implementing High Speed SPI4.2 Interfaces Using FPGAs
9:20am - 10:00am
1-TA2: CPU/DSP Combo Chip Handles Embedded Workloads
1-TA2: CPU/DSP Combo Chip Handles Embedded Workloads
10:10am - 10:50am
1-TA3: Soft Error Radiation Test, Simulation and Protection in Nanometer Technologies
1-TA3: Soft Error Radiation Test, Simulation and Protection in Nanometer Technologies
11:00am - 11:40am
1-TA4: Raising the Level of Abstraction for Design and Verification: SystemC and System Verilog in a Multilanguage Environment
1-TA4: Raising the Level of Abstraction for Design and Verification: SystemC and System Verilog in a Multilanguage Environment
2:00pm - 2:40pm
1-TP1: Setting the Standard for Multi-Core SoC Debug and Trace
1-TP1: Setting the Standard for Multi-Core SoC Debug and Trace
2:50pm - 3:30pm
1-TP2: Designing Practical Bug Free Digital Data Synchronization Circuits Across Multiple Clock Domains; including DDR Data Handling.
1-TP2: Designing Practical Bug Free Digital Data Synchronization Circuits Across Multiple Clock Domains; including DDR Data Handling.
Wednesday, February 2
9:40am - 10:20am
1-WA2: Hard Coded or Simply Software: The Best of Both Worlds in Traffic Management
1-WA2: Hard Coded or Simply Software: The Best of Both Worlds in Traffic Management
2:00pm - 2:40pm
1-WP1: SystemVerilog Implicit Port Connections
1-WP1: SystemVerilog Implicit Port Connections
2:50pm - 3:30pm
1-WP2: Hardware Implementation of a Tree-based IP Lookup Algorithm for OC-768 and Beyond
1-WP2: Hardware Implementation of a Tree-based IP Lookup Algorithm for OC-768 and Beyond
Tuesday, February 1
10:10am - 10:50am
2-TA3: An Advanced Methodology for On-chip Passive Component Design and Optimization
2-TA3: An Advanced Methodology for On-chip Passive Component Design and Optimization
11:00am - 11:40am
2-TA4: "Fearless Partitioning": An Efficient Approach to the Challenges of a True Multi-chip Integration into a Single SOC
2-TA4: "Fearless Partitioning": An Efficient Approach to the Challenges of a True Multi-chip Integration into a Single SOC
2:50pm - 3:30pm
2-TP2: A Method for Analyzing Full Chip PI and EMI Using Prallel Processed PEEC Model
2-TP2: A Method for Analyzing Full Chip PI and EMI Using Prallel Processed PEEC Model
Wednesday, February 2
8:50am - 9:30am
2-WA1: Challenges to Silicon Modeling in the Nanometer Era
2-WA1: Challenges to Silicon Modeling in the Nanometer Era
9:40am - 10:20am
2-WA2: Three-Dimensional Integrated Circuits Overcome Technical Limitations Inherent to Systems-in-Package
2-WA2: Three-Dimensional Integrated Circuits Overcome Technical Limitations Inherent to Systems-in-Package
Tuesday, February 1
8:30am - 9:10am
3-TA1: Joint Study of Simultaneous Switching Noise and IO Return Current for a CMOS FPGA Package
3-TA1: Joint Study of Simultaneous Switching Noise and IO Return Current for a CMOS FPGA Package
9:20am - 10:00am
3-TA2: Z-Axis Power Delivery: Concept and Implementation
3-TA2: Z-Axis Power Delivery: Concept and Implementation
10:10am - 10:50am
3-TA3: 90nm Low Power Implementation of ARM1136JF-S Test Chip
3-TA3: 90nm Low Power Implementation of ARM1136JF-S Test Chip
11:00am - 11:40am
3-TA4: Lower Power DRAM: Design Implications and Opportunities
3-TA4: Lower Power DRAM: Design Implications and Opportunities
Wednesday, February 2
9:40am - 10:20am
3-WA2: Power and Timing Closures for IC and Package Co-Design
3-WA2: Power and Timing Closures for IC and Package Co-Design
2:00pm - 2:40pm
3-WP1: Design of a Low-Power Differential Repeater Using Low Voltage Swing and Charge Recycling
3-WP2: Co-Design in the PA-8800 Microprocessor
3-WP1: Design of a Low-Power Differential Repeater Using Low Voltage Swing and Charge Recycling
3-WP2: Co-Design in the PA-8800 Microprocessor
Tuesday, February 1
8:30am - 9:10am
4-TA1: Development of a 10 Gb I/O Connector System
4-TA1: Development of a 10 Gb I/O Connector System
10:10am - 10:50am
4-TA3: Design of Embedded Capacitors in PCBs and Organic Chip Packages using Ultra-Thin Substrates
4-TA3: Design of Embedded Capacitors in PCBs and Organic Chip Packages using Ultra-Thin Substrates
11:00am - 11:40am
4-TA4: Embedded Passives in Boards and Packages: Case Study on Embedded Resistor Design and Cost Impact
4-TA4: Embedded Passives in Boards and Packages: Case Study on Embedded Resistor Design and Cost Impact
2:00pm - 2:40pm
4-TP1: Hybrid Stripline Analysis II: Propagation Characteristics, Crosstalk Effects and PCB Routability
4-TP1: Hybrid Stripline Analysis II: Propagation Characteristics, Crosstalk Effects and PCB Routability
2:50pm - 3:30pm
4-TP2: The Impact of PCB Laminate Weave on the Electrical Performance of Differential Signaling at Multi-Gigabit Data Ratesx
4-TP2: The Impact of PCB Laminate Weave on the Electrical Performance of Differential Signaling at Multi-Gigabit Data Ratesx
Tuesday, February 1
8:30am - 9:10am
5-TA1: Features and Implementation of High-Performance 667Mbs and 800Mbs DDRII Memory Systems
5-TA1: Features and Implementation of High-Performance 667Mbs and 800Mbs DDRII Memory Systems
9:20am - 10:00am
5-TA2: Connector-Less Probing - Electrical and Mechanical Advantages
5-TA2: Connector-Less Probing - Electrical and Mechanical Advantages
10:10am - 10:50am
5-TA3: 10 Gigabit Channel Virtual Design Kit
5-TA3: 10 Gigabit Channel Virtual Design Kit
11:00am - 11:40am
5-TA4: Employing LVDS Chips to Optimize FPGA Interface Performance
5-TA4: Employing LVDS Chips to Optimize FPGA Interface Performance
Wednesday, February 2
9:40am - 10:20am
5-WA2: Characterization and Production Test for CEI-6G-LR Compliant 6.25Gbps SerDes
5-WA2: Characterization and Production Test for CEI-6G-LR Compliant 6.25Gbps SerDes
2:00pm - 2:40pm
5-WP1: Novel Signal and Power Integrity Approaches: High Performance Backplane/Mezzanine Interconnects and Decoupling Interposers
5-WP1: Novel Signal and Power Integrity Approaches: High Performance Backplane/Mezzanine Interconnects and Decoupling Interposers
Tuesday, February 1
9:20am - 10:00am
6-TA2: 10Gb/s Receive Equalization for High Loss Backplanes
6-TA2: 10Gb/s Receive Equalization for High Loss Backplanes
10:10am - 10:50am
6-TA3: The Recessed Probe Launch - A New Signal Launch for High Frequency Characterization of Board Level Packaging
6-TA3: The Recessed Probe Launch - A New Signal Launch for High Frequency Characterization of Board Level Packaging
11:00am - 11:40am
6-TA4: Optimized Signal Path for Orthogonal System Architectures
6-TA4: Optimized Signal Path for Orthogonal System Architectures
2:00pm - 2:40pm
6-TP1: Using Equalization and Crosstalk Cancellation to Enable Next-Generation Throughput Rates on Legacy Backplane Systems
6-TP1: Using Equalization and Crosstalk Cancellation to Enable Next-Generation Throughput Rates on Legacy Backplane Systems
Wednesday, February 2
8:50am - 9:30am
6-WA1: Investigating Microvia Technology for 10Gbps and Higher Telecommunication Systems
6-WA1: Investigating Microvia Technology for 10Gbps and Higher Telecommunication Systems
9:40am - 10:20am
6-WA2: Impact of Manufacturing Parametric Variations on Backplane System Performance
6-WA2: Impact of Manufacturing Parametric Variations on Backplane System Performance
2:00pm - 2:40pm
6-WP1: Beyond 10Gbps: Next Generation Serial Interfaces
6-WP1: Beyond 10Gbps: Next Generation Serial Interfaces
Tuesday, February 1
8:30am - 9:10am
7-TA1: Test Socket Influence on High Speed Differential Signals and Channel Performance
7-TA1: Test Socket Influence on High Speed Differential Signals and Channel Performance
9:20am - 10:00am
7-TA2: A Discussion of Rj/Dj Compliance Measurement and What To Do When You Don't Hit Your Numbers
7-TA2: A Discussion of Rj/Dj Compliance Measurement and What To Do When You Don't Hit Your Numbers
11:00am - 11:40am
7-TA4: Total Jitter Measurement at Low Probability Levels, using Optimized BERT Scan Method
7-TA4: Total Jitter Measurement at Low Probability Levels, using Optimized BERT Scan Method
2:00pm - 2:40pm
7-TP1: Digital Engineer to Signal Integrity Engineer in 28 Hours
7-TP1: Digital Engineer to Signal Integrity Engineer in 28 Hours
2:50pm - 3:30pm
7-TP2: Eye Pattern Measurements on Scopes
7-TP2: Eye Pattern Measurements on Scopes
Wednesday, February 2
8:50am - 9:30am
7-WA1: Precision Jitter Transmitter
7-WA1: Precision Jitter Transmitter
9:40am - 10:20am
7-WA2: Edge-Optimized Equalization Extends Performance in Multi-Gigabit Serial Signaling
7-WA2: Edge-Optimized Equalization Extends Performance in Multi-Gigabit Serial Signaling
2:00pm - 2:40pm
7-WP1: Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications
7-WP1: Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications
2:50pm - 3:30pm
7-WP2: Addressing the Challenges of Implementing an At-Speed Production Test-Cell for 10Gb/s Wafer Probing
7-WP2: Addressing the Challenges of Implementing an At-Speed Production Test-Cell for 10Gb/s Wafer Probing
Tuesday, February 1
2:00pm - 2:40pm
8-TP1: Resolving EMI Problems with Good Power Delivery Strategy
8-TP1: Resolving EMI Problems with Good Power Delivery Strategy
2:50pm - 3:30pm
8-TP2: Modeling and Correlation of Supply Noise for a 3.2GHz Bidirectional Differential Memory Bus
8-TP2: Modeling and Correlation of Supply Noise for a 3.2GHz Bidirectional Differential Memory Bus
Wednesday, February 2
9:40am - 10:20am
8-WA2: Characterizing and Modeling the Impact of Power/Ground Via Arrays on Power Plane Impedance
8-WA2: Characterizing and Modeling the Impact of Power/Ground Via Arrays on Power Plane Impedance
2:00pm - 2:40pm
8-WP1: Measurements of Impedance, Current and Worst-case Noise on Chip Power Delivery System under Operating Conditions
8-WP1: Measurements of Impedance, Current and Worst-case Noise on Chip Power Delivery System under Operating Conditions
2:50pm - 3:30pm
8-WP2: High Performance FPGA Bypass Filter Networks
8-WP2: High Performance FPGA Bypass Filter Networks
Tuesday, February 1
8:30am - 9:1 0am
9-TA1: Automatic Verification of Timing Constraints
9-TA1: Automatic Verification of Timing Constraints
9:20am - 10:00am
9-TA2: Modeling Data and Transactions in SystemVerilog
9-TA2: Modeling Data and Transactions in SystemVerilog
10:10am - 10:50am
9-TA3: Maximizing Synergies of Assertions and Coverage Points within a Coverage-Driven Verification Methodology
9-TA3: Maximizing Synergies of Assertions and Coverage Points within a Coverage-Driven Verification Methodology
11:00am - 11:40am
9-TA4: Bringing Formal Property Verification into the Mainstream
9-TA4: Bringing Formal Property Verification into the Mainstream
2:50pm - 3:30pm
9-TP2: Creating a Provably Correct Design Methodology
9-TP2: Creating a Provably Correct Design Methodology
Wednesday, February 2
9:40am - 10:20am
9-WA2: Top-Down Post-Layout Mixed-Signal Design Verification Methodology for FPGA-Embedded Multi-Gigabit Transceiver
9-WA2: Top-Down Post-Layout Mixed-Signal Design Verification Methodology for FPGA-Embedded Multi-Gigabit Transceiver
2:00pm - 2:40pm
9-WP1: Design Illumination
9-WP1: Design Illumination
2:50pm - 3:30pm
9-WP2: Deriving Physical Design Understanding Through an Integrated Physical Debug Approach.
9-WP2: Deriving Physical Design Understanding Through an Integrated Physical Debug Approach.
Tuesday, February 1
8:30am - 9:10am
10-TA1: The Risks of Shipping Intellectual Property Offshore: What the EDA Industry Should Consider When Outsourcing Offshore
10-TA1: The Risks of Shipping Intellectual Property Offshore: What the EDA Industry Should Consider When Outsourcing Offshore
9:20am - 10:00am
10-TA2: Design for Manufacturing: What Designers Need to Know About the Coming Change in Yield Management
10-TA2: Design for Manufacturing: What Designers Need to Know About the Coming Change in Yield Management
10:10am - 10:50am
10-TA3: Outsourcing Designs for Nimble Product Development
10-TA3: Outsourcing Designs for Nimble Product Development
11:00am - 11:40am
10-TA4: Impact of Diagonal Routing Architecture on Traditional Cost vs. Performance Trade-offs in Digital IC Design
10-TA4: Impact of Diagonal Routing Architecture on Traditional Cost vs. Performance Trade-offs in Digital IC Design
2:00pm - 2:40pm
10-TP1: Your Customers Success is Your Success
10-TP1: Your Customers Success is Your Success
2:50pm - 3:30pm
10-TP2: A Process for IP Protection
10-TP2: A Process for IP Protection
Wednesday, February 2
8:50am - 9:30am
10-WA1: Towards Automation of IP Reuse Quality Measurement
10-WA1: Towards Automation of IP Reuse Quality Measurement
9:40am - 10:20am
10-WA2: The use of Quality Metrics in Effective IP Selection
10-WA2: The use of Quality Metrics in Effective IP Selection