Today's electronics manufacturers are keenly interested in delivering power-efficient designs right to market: the right feature set with the right power and performance at the right time and cost. The increased need for power-efficient design is forcing system and chip designers, alike, to think about power management and power integrity earlier and more often in the design flow, and to collaborate more closely with vendors throughout the designs. To enable their latest innovations -- from ultra-small video phones to multimedia gaming appliances to power-efficient broadband switchers and routers -- designers are increasingly looking to the technologists in their design chain for solutions to their power challenges. They are looking for advanced SoC, EDA, foundry and IP solutions to enable fast, power-efficient design at 130 nanometers and below. They are looking for the power to innovate. The power to reduce energy consumption, to mitigate heat problems, to remove power integrity issues such as voltage-drop and electromigration early in the design cycle.

This panel offers attendees the opportunity to hear executive experts discuss the critical need for collaborative advancements in power management and power integrity solutions, and provides a forum for questions-and-answers. Executive panelists from the leading SoC, EDA, IP and foundry providers will each briefly share how they are collaboratively addressing the need for power management and power integrity sign-off. They will then discuss what's needed in the near future to ensure 65-nanometer design success. This 30-minute executive presentation-and-discussion time will be followed by a 30-minute open-mic question-and-answer session.

Panel Moderator
Gary Smith
Chief Analyst
Gartner Dataquest

Mr. Smith is a chief analyst in Gartner Dataquest. Prior to joining Gartner, Mr. Smith was a consultant in design methodology. Before that, he was at LSI Logic, where he became involved in the development of the RT level design methodology. Starting in the semiconductor industry, Mr. Smith was involved in some of the first attempts at customer-designed ICs. He is a current member the Design TWG for the International Semiconductor Road Map (ITRS).

Panelists
Keith Clarke
Vice President of Engineering
ARM

Mr. Clarke graduated with a B.Eng (Hons) from Southampton University, UK in 1989 and then spent 3 years designing ASICs for the aerospace industry. He has been working at ARM since 1993, initially on ASICs and then was part of the team that developed the ARM7TDMI processor. In 2000 he became Manager of the CPU group in Cambridge, UK and in 2003 became VP Engineering. He is a Chartered Member of the IEE.

Antun Domic
Senior Vice President and General Manager, Implementation Group
Synopsys

Dr. Domic joined Synopsys in April of 1997. In his current position, he manages the Implementation Group, responsible for Synopsys' flagship synthesis and physical design solutions, test automation, signal integrity, power analysis and timing and formal verification products. Dr. Domic holds a Ph.D. in Mathematics from the Massachusetts Institute of Technology and a B.S. from the University of Chile.

Peter Henry
Vice President, Portable Power Systems
National Semiconductor

Mr. Henry is vice president of National Semiconductor Corporation's Portable Power Systems product line. He has directed the group since its establishment in 2000 and is responsible for product development, market strategy and silicon for this strategic market segment which focuses on maximizing battery life in wireless devices. Mr. Henry joined National Semiconductor in 1998 as director of design for the power management product line. Prior to National, he was the vice president of marketing for Suni Imaging Systems and held a variety of positions at Analog Devices, Inc. Mr. Henry earned his Bachelor of Arts Degree in Physics from the University of California, Berkeley. He completed the Stanford AEA Executive Institute in 1999.

Dave Heacock
Vice President, Portable Power Management Business, High Performance Analog (HPA)
Texas Instruments

Mr. Heacock is vice president of the portable power management business at Texas Instruments Incorporated. Prior to the merger with TI, he was the director for portable power products at Unitrode Corporation. Mr. Heacock was with Benchmarq Microelectronics from 1990 until the Unitrode acquisition in 1998. He has more than 17 years experience working in the area of battery management and low-power semiconductor products, and has a patent in battery capacity monitors. Mr. Heacock holds a bachelors of science degree in interdisciplinary engineering and management from Clarkson University and a masters of business administration in finance from the University of North Texas.

Ming Hsu
Director IP Management
UMC

Mr. Ming Hsu is responsible for working with IP partners to provide silicon-proven solutions to UMC customers. Prior to joining UMC, Mr. Hsu held various management and engineering positions at Systonics Inc., Clear Logic, Lattice Semiconductor, and IDT. He received a B.S. degree in Materials Science Engineering from National Tsing Hue University in Taiwan, and an MSEE from University of Southern California.