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Previous DesignCons: 2005
2005 Archive
Highlights | Schedule | Exhibitor List

Complimentary Programming
DesignCon offers a rich selection of free educational programs that provide you with a multitude of opportunities to sample DesignCon's quality education. Attendees are welcome to attend Keynote Addresses, Plenary Panels and Conference Panels at no cost.

Featured Keynote Speakers

January 31 | Monday Keynote Luncheon Address

Michael Fister
President & CEO
Cadence Design Systems, Inc.

February 1 | Tuesday Keynote Address

Aart de Geus
Chairman and Chief Executive Officer
Synopsys

Since co-founding Synopsys in 1986, Dr. de Geus has expanded the company from a start-up synthesis enterprise to an electronic design automation (EDA) industry leader. Named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 1999, he is the third recipient ever to receive the IEEE Circuits and Systems Society Industrial Pioneer Award. In 2002, Electronic Business Magazine named him CEO if the Year; in 2004, he was named Entrepreneur of the Year for Northern California by Ernst & Young. Heavily involved in education for the next generation, he created the Synopsys Outreach Foundation in 1999. He is Chairman of the Board for the Silicon Valley Manufacturing Group and a member of the board of directors of the Electronic Design Automation Consortium.

February 2 | Wednesday Keynote Address

Walden (Wally) Rhines
Chief Executive Officer and Chairman of the Board of Directors
Mentor Graphics

Dr. Rhines is President and Chief Executive Officer of Mentor Graphics, a leader in worldwide electronic design automation with revenue of over $510 million in 1999. Prior to joining Mentor Graphics, Rhines was Executive Vice President in charge of Texas Instruments' Semiconductor Group with responsibility for over $5 billion of revenue and over 30,000 people. He is on the board of directors of the Electronic Design Automation Consortium (EDAC) and a board member for the Oregon Independent College Foundation and of Lewis and Clark College. He also serves on the boards of Cirrus Logic and Triquint Semiconductor.


February 2 | Plenary Panel | 10:30 am - 11:45 am
Design Verification: From Specification to Closure

Panel Chair
Sergio Camerlo, Director of Engineering, Cisco Systems

Panelists:
Dhrumil Gandhi, Senior Vice President of Product Technology, Artisan Components, Inc
Yaron Kashai, Vice President, Research and Strategic Technology, Verisity Design
Sudhakar Sabada, Vice President, LSI Logic's Design Technology Group
Joe Sawicki, Vice President and General Manager, Design-to-Silicon Division, Mentor Graphics
Ronnie Vasishta, Vice President, Marketing, eASIC


Conference Panels
Panel discussions on current issues facing design engineers conclude each day of session programming. Each panel brings together experts on the selected topic for a lively and informative discussion. The following complimentary panels have been organized for DesignCon 2005:

January 31 | 4:45 pm - 6:00 pm
Jitter Characterization and Test of Serial Designs
Panel Chair: Chris Loberg, Design and Manufacturing Market Segment Manager, Tektronix

Bypass Capacitors: How to Determine Their Inductance
Panel Chair: Istvan Novak, Senior Staff Engineer, Sun Microsystems

February 1 | 3:45 pm - 5:00 pm
ASICs Dive into Mainstream Applications
Panel Chair: Bryan Lewis, Director and Chief Analyst, Gartner Dataquest
Organized by VSI Alliance
Taking the Pain out of Verification: Exploring What has to Change and Why
Organized by Francine Bacchini, Partner, ThinkBold Communications
Panel Chair: Gary Smith, Chief Analyst, Gartner Dataquest

Emerging PCB Laminates
Organized by Dave Brunker, Technical Fellow, Molex
Panel Chair: Dave Brunker, Technical Fellow, Molex

February 2 | 3:45 pm - 5:00 pm
OpenAccess: Creating State-of-the-Art EDA Tools and Design Flows
Organized by Si2
Panel Chair: Sumit DasGupta, Vice President, Silicon Integration Initiative (Si2)
The Trade-Offs of Software Programmability in Video Processors
Organized by Jonah Probell, Founder & Principal Design Engineer, Ultra Data
Panel Chair: Jonah Probell, Founder and Principal Design Engineer, Ultra Data
Are We Spending Our Verification Resources Wisely?
Organized by Brian Bailey; David Whipp, NVIDIA
Panel Chair: Brian Bailey, Functional Verification Consultant