Have you ever wondered why the same size bypass capacitor is listed with different inductance from different vendors? Do you want to know how some of the major OEMs want the inductance to be determined? Are you interested in knowing how major capacitor vendors measure the inductance? As a follow-up to the TecForum "Inductance of Bypass Capacitors: How to Define, How to Measure, How to Simulate?", this panel will discuss the views of OEMs and capacitor vendors on how to provide inductance numbers such that designers can readily use them. After a few minutes of presentations from each panelist, the floor will be open for discussion.
Panel Chair
Istvan Novak
Senior Staff Engineer, Sun Microsystems
In addition to signal integrity design of high-speed serial and parallel busses, Mr. Novak is a engaged in the design and characterization of power-distribution networks and packages for SUN servers. He creates simulation models, and develops measurement techniques for power distribution. Istvan has twenty plus years of experience with high-speed digital, RF and analog circuits, and system design.
Panelists
Mark A. Alexander
Product Applications Engineer, Advanced Products Division, Xilinx, Inc.
Mr. Alexander is involved in the creation of design rules and methodologies for power integrity assurance in large FPGA systems, at the die, package, and PCB levels. He has been with Xilinx for 6 years, and has previously worked in areas of PCB design for signal integrity and multi-gigabit transceiver physical media attachment.
Chris Burket
Senior Applications Engineer, TDK
Mr. Burket has worked for TDK since 1995 in various roles and now is a Senior Applications Engineer with an emphasis on technical applications and product marketing with Semiconductor companies. Prior to his TDK experience, he designed cockpit instrumentation for various aerospace companies.
Sergio Camerlo
Director of Engineering, Cisco Systems
Mr. Camerlo's current organization is strongly focused on high-speed interconnects and advanced packaging technology and its application to the next generation products. Sergio's work on signal, timing, power integrity, and high-speed backplanes layout engineering has been successfully applied to several products currently in production. He is also chairing the Cisco Switching Patent Committee and is involved with the industry and academia to foster the development of new high-speed interconnects and packaging materials and methodologies.
Hideki Ishida
Sanyo
Mr. Ishida started his career as an engineer of cylinder for VTR. In 1998, he joined the development team of polymer tantalum capacitors named "POSCAP" and currently manages application engineering team of POSCAP. He is also working to standardize measurement of ESR and ESL in the Japan Electronics and Information Technology Industries Association.He is a leader of the working group of the measurement method of ESR and ESL
Leigh Wojewoda
Intel
Ms. Wojewoda joined Intel Corporation in 1997 and has been working the field of computer packaging. She currently manages an electrical characterization lab specializing in measurement of capacitor performance. She has worked with several capacitor manufacturers on development of characterization techniques for package decoupling capacitors.
Zhiping Yang
Senior Signal-Integrity Engineer, Data Center, Switching, Wireless (DSW) Technology Group, Cisco Systems
Dr. Yang's work is focused on signal integrity and power integrity in high-speed digital system design. His current responsibilities include the power integrity methodology development for die/package/board co-design; signal-integrity design and analysis for ASIC, package, and PCB boards; and UHS differential signaling for backplane applications. He holds a Ph.D. in electrical engineering from the University of Missouri-Rolla.