Our industry's myth de jour claims that designers can write any kind of code, black-box it, and then throw it at lots of simulation to find all bugs. But in reality, even big companies with virtually infinite CPUs and engineers can't live up to the myth because simulation just is not enough to find all bugs. Functional bugs continue to invade silicon in an alarming number of ASIC and SoC designs.
Although the reconvergent model of verification (that is, a clear separation of design and verification teams) is critical as a checks-and-balances approach to flush out potential misinterpretations of the design specification, the question remains: Has this model reduced designer responsibility? Should we cease checking for flaws after-the-fact and move to a verify-as-you-design model? And if so, what tools and methodologies would support such a new paradigm?
This panel of visionaries and industry leaders will explore how we got to where we are today and what needs to change to take the pain out of verification.
Panel Moderator
Gabe Moretti
Technical Editor, ASIC and EDA, EDN Magazine
From 1968 to 1982, Mr. Moretti developed CAE software for TRW Systems, Compucorp, Intel, and Philips/Signetics. Over the next 18 years, he worked for EDA companies, from small start-ups to his own CAE service company, finishing with Intergraph/VeriBest for the last seven years. During his career, Mr. Moretti participated in the development of some lasting industry standards: the Pascal programming language, the VME bus, VHDL and Verilog hardware description languages, and the open model interface for digital simulation models. Mr. Moretti now writes about ASICs and the EDA industry and maintains an active role in EDA standard-making efforts from his home base.
Panelists
Harry Foster
Chief Methodologist, Jasper Design Automation
Mr. Foster serves as Chairman of the Accellera Formal Verification Technical Committee, which is currently defining the PSL property specification language standard. He is co-author of the new Kluwer Academic Publishers book Assertion-Based Design, as well as the Kluwer book Principles of Verifiable RTL Design. Prior to joining Jasper Design Automation, Harry was Verplex Systems' Chief Architect. Foster has researched and developed formal verification tools and methodologies for over 12 years as a Senior Member of the CAD Technical Staff at Hewlett-Packard, and is the original creator of the Accellera Open Verification Library (OVL) assertion monitor standard.
John Goodenough
Director, Design Technology, ARM Ltd.
Dr. Goodenough is responsible for all aspects of design flow supporting IP design deployment and integration. He has a long-standing interest in reusable and deployable verification techniques to support IP in the field, in addition to managing the challenges of the CPU verification escalator. Dr. Goodenough serves as a board member for OSCI and Accellera and takes a keen interest in the evolution of the verification ecosystem.
Kevin Normoyle
Architect, Azul Systems
Kevin Normoyle has been involved in CPU design, verification and system debug for over 20 years.He is currently an architect at Azul Systems, delivering network attached processing systems with as many as 384 cpus. Before that, he was at Sun Microsystems for 10 years, where as lead architect for the i-series UltraSparc processor design group, he learned a lot about what makes designs, chips and teams work or not work. He has been part of chip design and verification teams ranging from 5 people to 150 people.
Andrew Piziali
Senior Product Engineer, Verisity Design
Mr. Piziali has been practicing design verification since 1981, primarily in CPU design. He verified S/370 mainframes of STC Computer Research and Amdahl, supercomputers of Evans and Sutherland and Convex Computers, and x86 microprocessors of Cyrix, Texas Instruments and Transmeta. He is currently responsible for advanced product introduction at Verisity Design and continues to pursue his interests in coverage measurement and generation.
Harry Stuimer
Senior Staff Engineer, Sun Microsystems
Mr. Stuimer, Senior Staff Enginner, Sun Microsystems, has been involved in CPU design verification and silicon debug for over 10 years. He is currently solving design/verification challenges for future SPARC Processors. Prior to that, he managed the verification and silicon debug of the UltraSPARC IIIi, and contributed to the verification and bringup of a number of other CPUs at both Sun Microsystems and Intel. He is a proponent of verify-the-chip-any-way-you-can, and he and his teams are currently struggling with how to best incorporate emerging and often diverging technologies and tools into a coherent verification methodology.