Successful ASIC design has been hindered time and time again by market challenges. The roadblocks include high NREs, accelerating design complexity, time-to-market challenges, and shrinking design-time predictability. Is it really possible, after all these years, that ASICs can finally be viewed as viable silicon platforms for other than very high volume and bleeding-edge use, and be seriously considered for mainstream applications? If so, what needs to occur for this to happen? Our panelists will debate the reality that has hindered ASICs in the past and discuss the promise for midstream-application ASIC 'respect' in the future.

Panel Chair
Bryan Lewis, Director and Chief Analyst, Gartner Dataquest

Mr. Lewis is a research vice president and chief analyst for Gartner Research. He joined Dataquest in 1985 and founded Dataquest's ASIC/ SOC/ FPGA research. He has responsibility for tracking and evaluating market movements, forecasting markets, and tracking technology trends. Mr. Lewis is a key speaker at numerous conferences and consults with a wide range of worldwide clients.

Panelists
Richard Marz, Executive Vice President, Strategic Marketing, LSI Logic

Mr. Marz is responsible for the development and coordination of LSI Logic's global customer, channel, product and technology strategies in the company's target markets, including Communications, Consumer and Storage Components. Previously, Marz was LSI Logic's executive vice president of ASIC Technology, overseeing the company's ASIC design methodology, technology marketing and global design center resources. Earlier, Marz served as LSI Logic's executive vice president of Geographic Markets, managing the company's worldwide sales, distribution, ASIC design and Mint Technology activities. Prior to joining LSI Logic in 1995, Marz was vice president of Sales and Marketing for the Americas for Advanced Micro Devices, Inc. During his 18 years at AMD, he held a variety of executive and sales management positions. Marz also served as vice president and general manager of Cramer San Francisco for Cramer Electronics Corporation and Western Area manager at Motorola Semiconductor Products, Inc.

Michael Kaskowitz, Vice President and General Manager, Mentor Graphics, President, VSI Alliance

At Mentor Graphics, Mr. Kaskowitz is responsible for driving the company's strategy to deliver complete system-on-chip (SoC) solutions through the application of hardware and software IP. He brings 24 years of technology and management experience in the IP, embedded software and EDA industries to Mentor Graphics. Prior to joining Mentor Graphics, Mr. Kaskowitz served as vice president of engineering at Sensory, Inc. and, earlier, he served as vice president of engineering for Cadence Design Systems' Central Architecture and Technology, Flow Engineering, Product Engineering and Usability Engineering departments. He has also held positions with Compression Labs, Inc., VLSI, Motorola, and Apple Computer, Inc.

Naveed Sherwani, Co-Founder, President and Chief Executive Officer, Open-Silicon

Dr. Sherwani brings to Open-Silicon over 19 years of experience in technical engineering and general management. Prior to co-founding Open-Silicon, Naveed was the founder and General Manager of Intel Microelectronics Services. During his 9 year tenure at Intel, Naveed served in various technical and managerial positions. Naveed led various efforts to promote use of ASIC style methodologies to improve design efficiency and time-to-market. Naveed co-architected the Intel microprocessor design methodology and environment that has been used in various leading microprocessors. Prior to joining Intel, Naveed worked as a consultant for various telecommunications and computer companies, mainly focusing on ASIC style design flow and cell library design to improve time-to-market. He also served as a Professor at Western Michigan University, where his research concentrated on VLSI Physical Design Automation, combinatorics, and graph algorithms.

Ted Vucurevich, Chief Technology Officer, Cadence Design Systems

Mr. Vucurevich is responsible for driving advanced technology development and directing Cadence Laboratories. In addition, he serves as an executive fellow. He also co-leads the Strategic Technology Office (STO). The STO researches, plans, and promotes a world-class Cadence technology roadmap and vision to Cadence employees, customers, and analysts. As director of Cadence Laboratories, Mr. Vucurevich represents Cadence on various external boards and interfaces between research efforts and product development.

Ed Wan, Senior Director of Product Marketing, TSMC

Mr. Wan is currently the senior director of design services marketing of TSMC North America. Before joining TSMC, Mr. Wan was CEO of Spike Technologies, a leading chip design services company in Milpitas, California. Prior to Spike Technologies, he was vice president of worldwide field engineering of United Microelectronics Corporation, where he directed the internal design activities as well as the external network of library, IP, and design services providers. Mr. Wan also held the position vice president at Cadence, and vice president of engineering at LSI Logic, where he managed LSI Logic's North American design centers. He started his technology career as a circuit designer, product engineer, and applications engineer at Signetics.