As serial data rates increase from 1 Gb/s to 10 Gb/s, Signal Integrity design engineers must overcome the technical challenges of the system interconnect, package, power, and SerDes design. Case studies and research results are included in this paper to cover each topic. The case study examples were based on the author's design and trouble shooting experience of 1 Gb/s to 2.5 Gb/s designs. The research results were from feasibility studies of 10 Gb/s designs. Lab measurements and simulation data were used to analyze the impact to the signal quality.
This paper also presents the simulation challenges of 10Gb/s design. The lack of system simulation tools and good models made it very difficult to predict the real Bit-Error-Rate (BER). The conclusion is that the system simulation tools should include interconnects with 3D structure, SerDes package, SerDes circuit with PLL, and the power sub-system.