Ramin Hojati, Ph.D., President and Founder, Averant
Yen-min Chiu, Principal Developer, Averant

Incorrect timing constraints used to verify large complex digital circuits can leave designs with subtle, hard to find bugs. The ability to verify the correctness of such constraints is a powerful tool for insuring the proper timing and operation of modern, high-speed designs. This paper discusses a technique for verifying timing constraints using formal verification techniques.