Min Wang, Senior Signal-Integrity Engineer, Intel
Henri Maramis, Manager, Signal-Integrity Engineering, Intel
Donald Telian, Technologist, Cadence
Kevin Chung, Applications Engineer, PCB and Packaging Products, Cadence

Deficiencies in pre-hardware characterization of Multi-GigaHertz (MGH) serial links has caused a temporary return to hardware prototypes and testboards. Accurate MGH channel modeling is a challenge and, even if achieved, very CPU-intensive using current techniques. This paper details new concepts and technologies that enable a more thorough analysis of MGH serial links. Interconnect Storage Potential (ISP) is explained as a key to understanding the predictability of signal transmission, and the type of analysis required to arrive at an accurate eye diagram. The new methodology is illustrated using relevant serial interconnects such as PCI Express and Serial ATA.