Paul Aiken, Senior Test Engineer, Sort/Test Technology Development, Intel
Brahim Bensalem, Senior Test Engineer, Intel
Todd Albertson, Staff Test Engineer, Sort/Test Technology Development, Intel

In this paper, we present comparative high data rate analyses for OEM and various test sockets within desktop and server interconnecting environments. Three pairs of differential data are modeled for best and worst case conditions within the channels. Signal integrity gaps between OEM and test sockets are significantly reduced when equalization techniques are used. It is shown that socket influence on the signal integrity of the channel is very small with respect to that of the PCB traces, chip packages and vias. In many cases, costly upgrade to sockets may not significantly improve signal integrity of the channel.