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Previous DesignCons: 2005
2005 Archive
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6-TA2
10Gb/s Receive Equalization for High Loss Backplanes
Tuesday, February 1 | 9:20am - 10:00am

Riccardo Badalone, Chief Technology Officer, Diablo Technologies
John D'Ambrosia, Manager, Semiconductor Relations, Tyco Electronics

This paper details the design of a 10+ Gb/s equalizer optimized for serial binary data communications on high loss, high noise backplanes. The goal is to provide an equalization scheme that is adaptive, robust against elevated levels of crosstalk, and which does not rely on the transmitter to pre-equalize the data such that the maximum level of interoperability is achieved. Transistor-level simulation data using sophisticated models and worse case corners is presented to validate the approach.