Brock LaMeres, Ph.D. Candidate, University of Colorado
Sunil P. Khatri, Assistant Professor, Department of Electrical Engineering, Texas A&M University

This paper presents an analysis and method for selecting the size, speed, and package of an inter-chip digital bus. An analytical model is developed that describes the maximum data rate that an inter-chip bus can run and the cost effectiveness of the design. To verify the model, simulations are ran on three industry standard packages while varying the bus width, slew rate, and signal-to-power/ground ratio. The model formulates a selection and evaluation algorithm that can be used to optimize an inter-chip bus design for performance and cost. It is demonstrated that it is more cost effective to use faster narrower busses rather than slower wider busses to achieve a desired system throughput.