Lee Sledjeski, Applications Engineer, Communications Interface Division, National Semiconductor

Today FPGA vendors support at least some form of differential signaling capability. In the latest high-end offerings system designers have been making use of integrated multi-gigabit SERDES (serializer/deserializer) functionality. However, they have also been realizing the transmission line driving, PLL and CDR limitations of this integrated LVDS I/O and analog functionality. This paper will discuss the system tradeoffs between all-inclusive FPGA's and I/O optimized physical layer devices. The paper will show how smart system partitioning will improve reliability through lower overall power, higher ESD protection, and enhanced signal integrity. Specific application examples will be used to contrast the alternate solutions. The arguments will be supported with specification comparisons, layout diagrams, lab measurements, and simulation results when appropriate.