Dail Robert "Bob" Cox, Simulation Engineer, Micron Technology, Inc.
Randy Wolff, Simulation Engineer, Micron Technology, Inc.
Doug Burns, Chief Scientist and Vice President, Consulting, Signal Integrity Software
Barry Katz, President and Chief Technology Officer, Signal Integrity Software
Walter M. Katz, Chief Scientist, Signal Integrity Software

With ever-increasing CPU speeds, the need for higher bandwidth memory systems is greater than ever. With signaling rates up to 800 Mbs, DDRII memory technology provides the required bandwidth and growth path needed for current and next generation CPUs. Signal integrity, timing, and crosstalk analysis on these interfaces has become significantly more complex than for previous DDR technology. Historic analysis approaches do not properly calculate margin forcing costly over-design or over constraining of the system. This paper presents the unique challenges associated with DDRII memory design, new techniques that must be incorporated into the design methodology, discusses the details of proper waveform and timing calculation, and shows the analysis results for a standard 667 Mbs and 800Mbs DDRII reference design.