Yong Wang, Senior Electrical Engineer, Hewlett-Packard
Dave Quint, Master Engineer, Hewlett-Packard
Tim Michalka, Manager, Hewlett-Packard
Karl Bois, Expert Engineer, Hewlett-Packard

IC process scaling is leading high performance CPU designs to ever higher operating frequencies, lower power supply voltages, and higher power dissipation, using industry leading design and manufacturing technologies. For example, the ItaniumŪ processor Montecito features dual cores with 24 MB L2 cache memory. It operates at 1.2 V with a total power consumption ~100 W at ~2.0 GHz in a 90 nm process. This presents design engineers with great challenges in both IC design and power delivery system design, including power converter, power connector, package, and on-die power grid. Integrated power delivery system design, rather than compartmentalized design, is a critical strategy for successful CPU system design and performance evaluation, particularly with active power management. This paper comprehensively discusses accurate power measurement, the voltage feedback control loop, the VRM compensation loop, package design, and power delivery performance. The microprocessor performance goals also require several isolated power supplies, thus increasing design complexity and pushing the limits of packaging technology. The design trade-offs between different power supplies are also discussed. Modeling and simulation results along with measurements will be presented and discussed.