Carey Robertson, Product-Development Manager, IC Design and Verification, Mentor Graphics

The nanometer era has revealed significant concerns in signal integrity and timing closure in analog mixed signal designs. Physical effects are now the leading factor in the failure to achieve acceptable yield. However, current silicon-modeling techniques are unable to accurately predict if designs will successfully manufacture. Traditional methods of black boxing, assumptive device measurement and gate-level extraction are not sufficient to meet the accuracy requirements of simulating sophisticated IC designs. This is a task that can only be accomplished through exacting detail-actual device measurement and transistor-level parasitic extraction evaluated across the characteristics of the entire design.