This TecForum demonstrates the creation of a system-level, transaction-based testbench using VHDL. This approach creates a system-like environment by replacing each component of the system with either a bus functional model (BFM) or a full functional model (FFM). Tests are implemented in a separate model called the transaction controller. Multiple tests are created by having multiple architectures of the transaction controller. Each test consists of a sequence of transactions issued to one or more BFMs. Transactions for separate BFMs are driven from separate processes so the BFMs can operate independently from each other. These techniques can be applied to any hardware description language (HDL) or hardware verification language (HVL).