DesignCon Home
DesignCon 2006
Register Today
Home Conference Exhibition Exhibitor Info Sponsorship Press


Presented By
Official Sponsor
Diamond Sponsor
Gold Sponsor
Merchandise Sponsors
Hospitality Sponsor
Official Mangement Forum Sponsor
PCB Pavilion Sponsor
Official Public Relations Sponsor
Official Media Sponsor
Official News Service
Media Sponsors
Circuit Cellar
Connector Specifier
Connector Supplier
EDACafe
EG3
PCB007
Portable Design
System Design Frontier


Previous DesignCons: 2004
2004 Archive
Highlights | Schedule | Exhibitor List

Plenary Panel
Wednesday, February 4 | 10:15 am - 11:45 am
The Roadmap to 65 Nanometers: Design Needs and Technical Challenges
The International Technology Roadmap for Semiconductors has identified the technical challenges that must be met to reach the 65-nanometer technology node. This panel of executives representing companies spanning the semiconductor process flow, from design through fabrication and testing, will discuss how these challenges are being addressed at key points in the design chain. In addition to technical capabilities, panelist will also comment on designers' ability to utilize the processing potential available at this level of complexity, and the market need for such devices.

Chairperson
Greg Spirakis Greg Spirakis, Vice President, Mobile Platforms Group and Director, Design Technology Group, Intel.

Mr. Spirakis is responsible for the development and delivery of software technologies and tools for the computer-aided design (CAD) of silicon chips in all four of Intel's major architecture families. He joined Intel in 1982 as an EPROM reliability engineer and has since held a variety of technical and management roles, including positions as yield manager, design manager and Q&R manager. In 1997, Mr. Spirakis became director of design technology. He has received three Intel Achievement Awards.

Panelists

Ashok Sinha Dr. Ashok Sinha, Senior Vice President, Silicon Business Sector Products, Applied Materials

Dr. Sinha was named to his current position and a member of the Executive Committee in December 2000. He is responsible for the Si-Business Sector products. Since joining Applied Materials in 1990, Dr. Sinha has served in various positions, including managing director of technology for Applied Conductor Technologies (ACT) and general manager of the Metal Chemical Vapor Deposition (MCVD) division. Prior to joining Applied Materials, Dr. Sinha worked for 20 years at AT&T Bell Laboratories where he served as head of the VLSI Process Technology and Fabrication departments at Murray Hill and Allentown. He also served as vice president of manufacturing technology development at SEMATECH, a non-profit research and development consortium.

John Yue Dr. John Yue, Vice President of Technology, TSMC North America

A 30-year veteran of the semiconductor industry, Dr. John Yue is Vice President of Technology for TSMC North America in San Jose. Prior to that he was Vice President of Quality & Reliability for TSMC. Before joining TSMC, he worked at National Semiconductor, Texas Instruments and Advanced Micro Devices, where he was an AMD fellow. His areas of responsibility have included silicon materials research, product and process engineering, process integration, technology reliability, and quality engineering.

Charles J Rothschild Charles J. Rothschild, Automated Test Group Research and Development Manager, Agilent Technologies

Mr. Rothschild, new to this role in January 2004, is responsible for coordinating R&D programs across Agilent's Automated Test Group, which focuses on Semiconductor Test and Electronic Module Test. He is also responsible for Agilent technologies long-term research in these areas. Mr. Rothschild started his career at Hewlett Packard managing a wide variety of Research programs, including data acquisition systems, instrumentation systems, and spent 10 years on the computer side of HP developing UNIX based graphics terminals. He also served as the Research and Development Manager for Agilent's Flash Memory Test Business, including the Versatest line. Mr. Rothschild focuses on innovating high-volume test solutions throughout the semiconductor manufacturing value chain, addressing today's and future test challenges.

Antun Domic Dr. Antun Domic, Senior Vice President and General Manager, Nanometer Analysis and Test, Synopsys

Dr. Antun Domic joined Synopsys in April of 1997. In his current position, Dr. Domic manages the Implementation Group, responsible for Synopsys' flagship synthesis and physical design solutions, test automation, signal integrity, power analysis and timing and formal verification products. Dr. Domic holds a Ph.D. in Mathematics from the Massachusetts Institute of Technology and a B.S. from the University of Chile.