Chairperson
Christopher Loberg, Design and Manufacturing Market Segment Manager, Tektronix, is responsible for providing Tektronix' solution set for digital design validation, debug and standards compliance to the computer and semiconductor industries. In an earlier role with the company, Mr. Loberg was the product line marketing manager for the Optical Parametric Test Product Line at Tektronix, providing design support for companies developing high-speed optical technologies for telecommunications.
Panelists
Kevin Cai, Senior Staff Engineer, Sun Microsystems, is responsible for company-wide high speed interconnect technology in terms of copper/optical and passive/active solutions. Before joining Sun, Mr. Cai served different high speed/wireless system design and advisor positions with Nortel Networks.
Eric Kvamme, Manager and Principal Engineer, Maxtor, manages the Advanced Interface Engineering Group at Maxtor. He has more than 14 years experience in the mass storage industry with a focus on interface signal integrity. Mr. Kvamme authored the ATA/66, 100, and 133 extensions to the ATA/ATAPI specification and is a leading participant in the SATA Electrical, Jitter, and Measurement subcommittees.
Dr. Mike Li, Chief Technology Officer, Wavecrest, has more than 10 years experiences in high-speed related measurement instrumentation, testing, and analysis/modeling algorithms/tools, with applications in IC, microprocessor, clock, serial data communications for both electrical and optical, and wireless communication. He pioneered jitter separation method (Tailfit) and DJ, RJ, and TJ concept and theory formation.
Mark Marlett, Principal Design Engineer, LSI Logic, has been designing, validating and characterizing serial interface physical layer transceivers and phase locked loops for fibre channel, SONET, PCIE, SATA and data moving backplanes since 1991. After an MSEE in 1989 from University of Illinois Urbana-Champaign, Mr. Marlett started working at Cypress Semiconductor. He joined LSI Logic in 2003.
Andrew Martwick, Circuit Architect, Chipset Division, Intel, recently authored sections of the 3GIO physical layer specification and co-chairs the PCI Express Jitter Working Group. He has more than 20 years of product design experience in software, hardware and embedded systems, and more than 20 patents issued or pending in computer architecture and communications.
Ransom Stephens, Applied Electrodynamics Scientist, Agilent Technologies, specializes in the analysis of physical layer processes in high data rate systems. He spent thirteen years in basic research specializing in precise measurements of rare processes while working on experiments across the United States, from Stanford to Fermi Lab to Cornell, and in Europe, at CERN in Geneva. Mr. Stephens entered the private sector as director of advanced technology for a start-up company in 1999 and joined Agilent in 2001.
Ken Ferguson, Manager, Test Technology Engineering, PMC-Sierra, is responsible for finding creative solutions to test challenges. He spent 3 years in characterization and production test method development and yield enhancement for thin-film superconducting magnetic sensors (SQUIDs) with CTF Systems before joining PMC-Sierra in 1994 as a product engineer.
Jit Lim, Senior Technologist, Oscilloscope Applications, Tektronix, has extensive experience in oscilloscope manufacturing, hardware design, software design, and program management. Most recently, he was responsible for developing Tektronix' jitter analysis solutions and the fastest real-time oscilloscopes.