The bus functional model (BFM) verification strategy has proven to be very effective for slave IP modules, but lacks the adaptability to verify master IP modules. This paper explains the limitations of BFMs for master IP verification, and proposes a more effective verification strategy that uses smart BFMs, taking the stimuli to a higher level of abstraction. An ARm - based cryptographic processor is used to demonstrate the effectiveness of the proposed technique, which has reduced the verification learning curve for new engineers, and has allowed experienced engineers to concentrate on debugging the functionality of the design, instead of spending time understanding cumbersome test benches.