2004 Archive
Highlights | Schedule | Exhibitor List
2-TP1
Tuesday, February 3 | 2:00 pm - 2:45 pm
TLM Bus Verification for RTL Compliance
Petr Tomiczek, Senior Engineer, IP Integration, CoWare
Using transaction-level modeling (TLM) to capture a design specification, prior to modeling the design in RTL, can introduce many implementation details. Due to the higher simulation speed, TLM offers far more architectural exploration. Architectural and simulation accuracy of a TLM model can be a justifying factor for making the trade-off between a necessary modeling overhead on one hand and a higher simulation speed on the other. Simulation and architectural accuracy of TLM systems are heavily dependent on a TLM bus model. Accuracy, in fact, defines the reliability of analysis. Ideally, the overall system analysis results obtained from the TLM platform would be preserved when moving the design to RTL.




































