2004 Archive
Highlights | Schedule | Exhibitor List
11-TA1
Tuesday, February 3 | 9:00 am - 9:45 am
Design of a 6.25-Gbps Backplane SerDes with Top-Down Design Methodology
Song Wu, Senior Member of the Technical Staff, Texas InstrumentsSridhar Ramaswamy, Member of the Group Technical Staff, Texas Instruments
Bhavesh Bhakta, Member of the Group Technical Staff, Texas Instruments
Paul Landman, Distinguished Member of the Technical Staff, Texas Instruments
Robert Payne, Senior Member of the Technical Staff, Texas Instruments
Vikas Gupta, Member of the Group Technical Staff, Texas Instruments
Bharadwaj Parthasarathy, Member of the Group Technical Staff, Texas Instruments
Seema Deshpande, Program Manager, Texas Instruments
Wai Lee, Design Manager, Texas Instruments
SerDes design exceeding 6.25 Gbps for existing backplanes has to overcome significant signal-integrity challenges on channel attenuation, crosstalk, and multiple reflections. This paper presents a 6.25-Gbps backplane SerDes design adopting a top-down design methodology from system-level Matlab simulation down to transistor level spice simulation to optimize the architecture and design. The BER performance is predicted with a joint probability density function (PDF) to account for all the impairments at the decision slicer.