Backplane links operating in the 6-Gbps to 12-Gbps region are affected by a number of transmission channel impairments such as frequency-dependent losses, reflections, crosstalk, thermal noise, and environmental impulse noise. The authors of this paper describe a prototype backplane transceiver environment that combines equalization and error-correction coding (ECC, also known as FEC) to combat these impediments. The system is based on an Aeluros' 10Gb transceiver chip with TX-side equalization, together with an FPGA-based ECC implementation. The authors describe the system design and coding scheme in some detail and describe their stress test setup and results. Also, they discuss system-level issues such as decoding latency and overhead.