Complimentary Programming
The following activities are available to all attendees of both the conference and technology exhibition. If you are planning to visit the exhibits floor Tuesday or Wednesday, stop by today to pick up your attendee badge and enjoy this free programming.

Noon - 1:00 pm | Great America Ballroom Monday Keynote Address View Jan Rabaey's keynote address. (Windows Media Player required) Jan Rabaey Professor and Director, Gigascale Silicon Research Center University of California, Berkeley

Read the EDA Weekly article on Jan Rabaey's DesignCon keynote address.

4:15 pm - 5:30 pm
Conference Panels

OpenAccess Deployment and Adoption | Ballroom G Chairperson Jim Wilmore Research and Development Engineer Hewlett-Packard

Serial Design Test and Debug | Ballroom F Chairperson Christopher Loberg Design and Manufacturing Market Segment Manager Tektronix

Also on Monday
DesignCon TecForums: Half-day tutorials presented in both the morning and afternoon addressing key topics in an in-depth and interactive atmosphere.
View the on-line schedule for TecForum listings.

Technology Exhibition
The exhibit floor opens today with more than 100 companies from around the world offering hands-on demonstrations of the latest technologies affecting the EDA and semiconductor industries.
>>View the latest list of DesignCon exhibitors
>>View the hot technologies on display
Tuesday Exhibition Hours: 12:30 pm - 6:30 pm

Complimentary Programming
The following activities are available to all attendees of both the conference and technology exhibition.

Noon - 12:30 pm | Theater Tuesday Keynote Address Aart de Geus Chairman and Chief Executive Officer Synopsys

4:00 pm - 5:15 pm
Conference Panels

Establishing Pass-Fail Criteria for High-Speed Digital Interfaces | Ballroom F Chairperson Greg Edlund Senior Engineer, Signal Integrity Engineering and Technology Services IBM

Solving the Real Challenges of Low-Power SoC Design in 90 Nano... | Ballroom G Chairperson Tets Maniwa Editor-in-Chief Chip Design Magazine

Wireless Design Challenges | Ballroom H Chairperson Gabe Moretti Technical Editor, ASIC and EDA EDN Magazine

Also on Tuesday
A full program of technical sessions offer paper presentations hand-selected by the DesignCon Technical Program Committee.
>>View the on-line schedule for paper listings.

Technology Exhibition
The exhibit floor opens today with more than 100 companies from around the world offering hands-on demonstrations of the latest technologies affecting the EDA and semiconductor industries.
>> View the latest list of DesignCon exhibitors
>> View the hot technologies on display
Wednesday Exhibition Hours: 12:30 pm - 6:30 pm

Complimentary Programming
The following activities are available to all attendees of both the conference and technology exhibition.

10:30 am - 11:45 am | Theater Plenary Panel: The Roadmap to 65 Nanometers: Design Needs and Technical Challenges Chairperson Greg Spirakis Vice President, Mobile Platforms Group, and Director, Design Technology Group Intel

Noon - 12:30 pm | Theater Wednesday Keynote Address Tsugio Makimoto Corporate Advisor, Semiconductor Operations Sony Corporation

4:00 pm - 5:15 pm
Conference Panels

Acceptance of Next-Generation Verification Methods: Roadblocks and Enablers | Ballroom E Chairperson Gary Smith Chief Analyst Gartner Dataquest

Board and Package Level PDN Simulations | Ballroom F Chairperson Istvan Novak Senior Signal Integrity Staff Engineer Sun Microsystems

Also on Wednesday:

IEC Executive Forum @ DesignCon | Ballroom G
The IEC Executive Forum @ DesignCon is positioned to provide a unique educational opportunity to industry leaders. Executives will have the opportunity to meet, network, and trade knowledge and expertise in an interactive educational atmosphere. The Forum includes the three following panel discussions. Attendees of the Forum are also invited to the Plenary Panel and Keynote Address for a full day of programming.

9:00 am - 10:15 am FPGA vs. ASIC Design Chairperson David Bursky Editor-at-Large Electronic Design Magazine

2:30 pm - 3:45 pm EDA Licensing Models Chairperson Richard Tobias Vice President, ASIC and Foundry Business Unit Toshiba America Electronic Components

4:00 pm - 5:15 pm Leadership in Times of Change Mark Pierpoint Vice President, Marketing Agilent Technologies

Wednesday includes a second day of technical paper sessions.
View the on-line schedule for paper listings.