Highlights | Schedule | Exhibitor List

View the Nano TecForum wrap-up

Tuesday Highlights:

• The IEC announced two new DesignCon events to bring the unique and time-tested DesignCon educational program on practical design solutions to engineers in the Northeast region of the United States and central Europe. DesignConEast will be June 23-25, 2003, at the Boston Seaport Hotel in Massachusetts. EuroDesignCon will be held October 27-30, 2003, at the Sheraton Hotel in Munich, Germany.
• Chris Malachowsky, Co-Founder, NVIDIA, will present the keynote luncheon address, "The Visual Consequences of Moore's Law." This multimedia talk will focus on the historical progression of graphics systems, the semiconductor technology they were based on, and the types of visual experience they enabled.
• Gabe Moretti, Technical Editor, ASIC and EDA, EDN Magazine, is chairing a System-on-Chip Conference Panel titled "Can Anyone Really Afford to Test a Complex SoC."
• Dr. Henri Merkelo, Chief Executive Officer, atSpeed Technologies, is chairing a High-Performance Conference Panel titled "Advances in Active Signal Conditioning Technologies."
• Forty paper presentations from industry experts in the areas of System-on-Chip and ASIC Design and of High-Performance Systems Design.

Wednesday Highlights:

• Ron Nersesian, Vice President, Design Validation Unit, Agilent Technologies, is chairing a plenary panel on the "Challenges at 90 Nanometers." Panelsits include Mark-Eric Jones, Vice President and General Manager, Intellectual Property, MoSys; Ronnie Vasishta, Vice President, Technology Product Marketing, LSI Logic; and Ted Vucurevich, Senior Vice President, Office of the Chief Technology Officer, Cadence Design Systems.
• Ralph Cavin, Vice President, Research Operations, Semiconductor Research, will present the keynote luncheon address.
• Mike Li, Chief Technology Officer, Wavecrest, is chairing a High-Performance Conference Panel titled "Challenges in Designing/Verifying a 2.5 to 3.2 Gbps Time-Domain Transmission System."
• Phil Heine, Director, Strategic Business Development, Avnet Design Services, is chairing a System-on-Chip Conference Panel titled "Intellectual Property Cores - A Report from the Trenches."
• Eleven paper presentations from industry experts in the areas of System-on-Chip and ASIC Design, including tracks on Configurable and Reconfigurable Designs, SoC Design and Integration Challenges, Functional Verification, and High-Speed Validation at the Chip Level.
• Twenty-one paper presentations from industry experts on High-Performance Systems Design, including tracks on Multi-Gigabit System Design Challenges, New Limits for High Data-Throughput on Copper, High-Speed Validation, and High-Speed Timing.
• Complimentary session: A special panel, titled "Leadership in Times of Change: Keeping the Engineering Team's Skills and Tools Up to Date," chaired by Mark Pierpoint, Vice President, Agilent Technologies, will begin with a welcoming reception at 3:30 pm on Wednesday, January 29, which will be immediately followed by the panel presentation from 4:00 pm to 5:15 pm.