Event Highlights
DesignCon 2001 again proved to be Silicon Valley's leading design-engineering conference in featuring more than 100 sessions and keynote presentations in system-on-chip design, high-performance systems design, wireless and optical broadband design, and intellectual property. In addition, DesignCon featured its largest exhibit floor to date with more than 128 companies exhibiting. Professionals were able to meet face to face with exhibitors to discuss new product innovations and solutions and to see those innovations and solutions first-hand.
As the keynote speaker for the day, Walden Rhines, Chairman and CEO of Mentor Graphics, expanded upon what he called the "Age of Discontinuity." He provided examples of how the success of FPGAs has generated a demand for new tools that have the functional strength of ASIC design tools but at a fraction of their selling price. He also illustrated the recent strong demand for printed circuit-board design tools, which has followed a decade of an average of 15 percent growth. This growth was caused by higher-speed designs, advanced packaging (such as ball grid array), and more compacted boards. He discussed how system-on-chip has had a major discontinuity on timing closure. Furthermore, in the analog arena, there has been less analog design due to a shortage of analog designers, but mixed-signal design and the movement from traditional analog solutions to digital technology has offset this. Mr. Rhines concluded by stating that future progress in physical design would be evolutionary rather than discontinuous. The subwavelength crises are being addressed with phase shifting and optical proximity correction. Design complexity requires hierarchical techniques and parallel compute processing.
Bob Pease, Staff Scientist for Circuit Design, National Semiconductor, and monthly columnist, Electronic Design, entertained attendees during Tuesday evening's presentation with wit—proving that engineers really can have fun, too. Mr. Pease posed many questions including the following:
Is an RF transmitter or wireless receiver be considered an analog system? Is a bus running at 100 MHz be considered a bunch of analog signals and cross talks and reflections? Is an optical signal that has to be detected considered an analog problem? Are the limitations of one's systems be considered analog limitations? When you try to put your system into operation—or into production—can the problems that are generated be considered analog problems? He also discussed the way in which analog capabilities and weaknesses impact one's system design and how these weaknesses cannot be ignored. Because analog circuits are involved in many digital systems, one should not try to sweep them under the rug or to lock the designers of these circuits away in the proverbial attic.
Wednesday's keynote presentation from Charles Fox, President and CEO of Chameleon Systems, raised several eyebrows as he spoke on "The Coming Era of Field Programmability" (or "ASICs are Dead!") Mr. Fox pointed out that Shannon's Law, which expresses the increase in algorithmic complexity, is overshadowing advances in Moore's Law, and he gave 3G cellular Internet as the defining example of this. Also, he demonstrated how a multiplicity of 2.5G and 3G wireless modulation standards heighten the risk of building an ASIC. The chip's long development cycle and high cost of failure have critical implications for any design team. Current ASIC risk factors are the chip's design and tool complexity, its high mask set costs, the lack of ASIC engineers, and the necessity to change its design as standards evolve. The key problem is the high risk of failure and the impact on time-to-market if a chip must be "re-spun." Comparatively, field-adaptable technology needs only an hour for a respin, while an ASIC needs months.
Mr. Fox quoted H&Q in support of this:
[R]econfigurable computing technology will be a key trend reshaping the semiconductor industry in the twenty-first century . . . much in the same way that the microprocessor has reshaped the last three decades.
The challenge to reconfigurable platforms is to maintain performance, flexibility, and time-to-market while keeping power low. Because bit maps are the "programs" in these devices, chips can vary functionally to meet a demand of 10 and 20 milliseconds on the 3G time cycles. Chameleon Systems is advocating devices that reduce this time to microseconds or even nanoseconds. Performing only the functions necessary provides significant power savings. This platform is a "chip-on-demand" that meets the adaptable processing needs of 3G cellular Internet.
Jack Shandle, Chief Editor, e-chips, set the scene for Wednesday's plenary panel to review the impact of Internet technology on the delivery of EDA tools and services-how it has created both opportunities and challenges. In a presentation titled, "Design Engineering and the World Wide Web: Where They Meet to Create Ultimate Value," Mr. Shandle described the opportunities for global collaboration, access to domain expertise, infrastructure cost savings, and reduced compute time. He also pointed out the necessity for new partnerships, resources, and business models to take advantage of EDA opportunities. He presented the users first (David Burgoon of Hewlett-Packard and Mark Ross of Cisco Systems) and the vendors second (David Burow of Synopsys and Judy Owen of SiliconX).
Mr. Burgoon is applying Internet methods for system verification and productivity. He points out the potential for capacity-on-demand, outsourcing hardware, improved access, collaboration, shared databases, and version control. Challenges are changing existing infrastructure and new investment, security, reliability, and necessity to include in-house tailored customization. The value is in the user business case for improved time-to-market.
Mr. Ross is keenly interested in using Internet methods to improve productivity, time-to-market, quality, and process documentation. The challenges include the daunting task of considering the entire end-to-end process, the reluctance to embrace change, and the fact that EDA is often at the bottom of the food chain. He also points out a well-known problem—that engineers are tough customers; they have difficulty in expressing their needs. He proposes document control, knowledge bases, IP reuse, development tracks, and checklists.
Mr. Burow reviewed the ASP market. EDA, which accounts for 15 percent of the ASP market, is expected grow from $500 million today to $3 billion by 2003. The vendor's problem is licensing on demand and creating environments to support shared computer resources, large design data sets (10 Gbyte or more), data synchronization, a shortage of engineers, and the globalization of expertise. He provided an example of an intranet-hosted design environment (Design Sphere Architecture) with 50 engineers at the site providing design services and tools.
Ms. Owen described a free Web site with information and utilities—e.g., marketplaces, electronic catalogs (specifications, technical documentation, and intellectual property), data publishing and sharing, and parametric searches. The site supports collaboration and on-line design reviews. By providing a secure, reliable, information rich and support its users gain productivity. Overseas vendors are the largest participant types because the site allows them to establish a global presence. Ms. Owen's discussion focused on flexible licensing models, the ability to gain access to the right consultants, and tools for rapid prototyping. New pricing models are necessary, with lower cost expectations but larger numbers of customers. Remote access to tools is also necessary, but not presently in all licensing models. This requires changes in support and business models by vendors. Vendors need a price level that is consistent with the value added to the design-engineer market.