TFA1 Configurable Platforms—The ASIC Revolution
Cary Ussery, President and Chief Executive Officer, Improv Systems

TFA2 Changing the Verification Process
Frank Malloy, Senior Corporate Applications Engineer, Synopsys
Rajiv Maheshwary, Product Line Manager, Synopsys

TFA3 High Speed Interface Design: A Practical Approach
Mike Grabois, Member of Technical Staff, Paradyne

TFA7 System and I/O Buses Issues in High Speed Embedded Computing
Al Chame, Senior Applications Engineer, Motorola
Tom Wilson, Product Manager, Tundra Semiconductor
Roger Langlois, Manager, Physical Design Methodology, Tundra Semiconductor
Ahmed Khan, Senior Account Manager, CADSoft Solutions

TFA4 Principles of Verifiable RTL Design
Harry Foster, Senior Member of CAD Technical Staff, Hewlett-Packard
Lionel Bening, Senior Member of CAD Technical Staff, Hewlett-Packard

TFA5 Challenges of Wireless Home Networks and Cordless Telephones
Yoram Solomon, Vice President, Voyager Technologies

TFA6 An Introduction to DSL
Jonathan Y. Stein, Chief Scientist, RAD Data Communications

TFP1 Electrically Correct Design Techniques Bring Performance and Predictability, 2000
Dhiraj Sogani, Director of Marketing, Sapphire Design Automation

TFP2 Validating the RAMBUS™ Channel, AGP4X Bus, and Pentium III™ FSB Using TDR and Logic-Analysis Tools
Gregg Buzard, Program Manager, Hewlett-Packard
Mike Resso, Product Manager, Agilent
Jennie Grosslight Engineer, Hewlett-Packard

TFP3 Practical Object-Oriented Software Design and Technology Management Techniques
Alex Holland, President, Stellar Winds

TFP4 Design-Reuse Industry Direction: Applying OpenMORE to Assess the Reusability of IP Cores
Pierre Bricaud, Director of Marketing for IP, Mentor Graphics
Michael Keating, Director, Synopsis
Jean-Pierre Gueguen, Marketing Manager, Synopsis

TFP5 When Test Vectors Are Useless—Verifying IP–Based SoC Designs
Thomas L. Anderson, Vice President-Applications Engineering, 0-In Design Automation

TFP6 The Market Politics and Strategies for 3G Deployment
Tanveer ul-Haq, Member of Technical Staff, Lucent Technologies

Panel: High-Performance Backplane Design—Where Is It Headed?
Andrew Grace, Principal Engineer, Strategic Marketing, Fairchild Semiconductor

I211 Choosing a Memory Technology for SOC
Mark-Eric Jones, Vice President and General Manager of IP, MoSys

I221 Using Embedded Checkers to Solve Verification Challenges
Scott Switzer, President, SmartSand
David Landoll, Design Verification Consultant, 0-In Design Automation

W211 UMTS W–CDMA Technology Development Using an Integrated Design Methodology
Vincent J. Coli, Director-Product Marketing, Aptix

W221 3G Baseband Solutions for Subscriber Terminals Switching and High-Speed Data (DSP)
Tom Garvens, CDMA Systems Applications, Motorola

S212 Bus Structures Optimized for System-on-Chip
Amjad Qureshi, System-on-Chip Design Manager, Phoenix Technologies

S222 Hybrid DSP Architecture for Audio Applications
Manoz Krovvidy, Senior Design Engineer, VLSI Technology (a subsidiary of Philips Electronics) Scott Harrow, Staff Design Engineer, VLSI Technology

H211 Practical System Debugging Technique for 64-bit, 66-MHz PCI
Cary Snyder, Applications Engineering-IP MegaCore Group, Altera Corporation

H221 High-Performance Backplane Architecture
Lee Sledjeski, Senior Applications Engineer, Fairchild Semiconductor

I212 IP Integration and Customization for a Digital IO ASIC
Michal Siwinski, Applications Engineer, Verplex Systems
Ruchir Dixit, Design Engineer, Mentor Graphics
Jeffrey Eversmann, Design Engineer, Mentor Graphics

I222 Design and Verification Methodology for Developing (ASIC) IP in FPGAs
Ed Petryk, Director of Engineering, VLSI Technology (a Subsidiary of Philips Semiconductors)
Subbu Meiyappan, Senior Design Engineer, VLSI Technology

W212 Case Study on Achieving First-Silicon Success for a CDMA Handset ASIC through Reconfigurable System Prototyping
Greg Lara, Product Marketing Engineer, Aptix
Luis Aldaz, Project Manager, VLSI Technology Wireless Division

W222 Inverse Multiplexing over ATM (IMA) System Design—A Case Study
Ananda K.S., Senior Software Engineer, Wipro Infotech
Atul Mahamuni, Software Specialist, Wipro Limited

S213 Connecting Multisource IP to a Standard on-Chip Architecture
Bill Dittenhofer, Design Engineer, PalmChip

S223 Frequency Dependence of Resistance and Inductance Effects in on-Chip Interconnects
Li-Fu Chang, Member of Technical Staff, Frequency Technology
Keh-Jeng Chang, Member of Technical Staff, Frequency Technology
Robert Mathews, Member of Technical Staff, Frequency Technology
Christophe Bianchi, Member of Technical Staff, Frequency Technology
Ken Wong, Member of Technical Staff, Frequency Technology

H212 Optimizing I/O Performance in Embedded PCI Systems
Thomas W. Martin, Marketing Manager, PLX Technology

H222 Design Techniques for High-Frequency Serial Backplanes
Tom Palkert, Systems Engineering Manager, AMCC
Mike Sluyski, AMCC

I213 Using On-Chip Resources to Optimize Context Switching and DMA Solutions in Embedded RISC Systems
Ravi V. Addala, Member of Technical Staff, Motorola
Chinh H. Le, Director of Hardware Engineering, Realchip

I223 Verification of Lexra Processor Cores
Elliot Mednick, Processor Architect, Lexra
Charley Lind, Design Engineer, Lexra
Jonah Probell, Design Engineer, Lexra
Franklin Hooker, Design Engineer, Lexra
Bob Gelinas, Design Engineer, Lexra
Todd Snyder, Design Engineer, Lexra

W213 Dual Core Architecture for Cellular Handsets
David R. Gonzales, Senior Member Technical Staff (MTS), Motorola MicroCORE Technology

W223 SRAM Architecture for Network Applications
Rajesh Manapat, Senior Applications Engineer, Cypress Semiconductor Corporation

DesignCon 2000 Keynote Presentation

S214 VCI: A Standard for On-Chip Bus Interface
J. Sukarno Mertoguno, Staff Architecture Engineer, Fujitsu WWSLT

S224 DLL Design Enhances FIFO Performance in FPGAs
Wai-Leng Lim, Application Engineer, QuickLogic
John Birkner, Cofounder, QuickLogic

H213 Virtual Prototyping and Simulation-Assisted Hardware Verification Techniques
Daniel Notestein, President, SynaptiCAD
Gregg Buzard, Program Manager, Hewlett-Packard
Maria Lizarraga, Technical Support Engineer, Agilent

H223 Solutions for an Effective Backplane
Shankar Balasubramian, Applications Engineer, Texas Instruments
Ernest Cox, Senior Applications Technician, Texas Instruments

Panel: SoCs for the Consumer Market Require Integration of Analog/Mixed-Signal IP Blocks: The Challenges and Solutions for Delivering Real-World Interfaces (Hosted by the VSI Alliance)
Henry Chang, Services R&D Architecture Group, Cadence Design Systems

W214 Software-Definable Radio: Past, Present, and Future Mobile Wireless
Cherif Chibane, Advanced Wireless Technology Lab, Sony US Research Labs, SONY

W224 Versatile Modem Facilitates Cost-Effective ADSL Deployment
Al Chame, Senior Applications Engineer, Motorola

S215 Silicon Development Platform Simplies System Design
Curtis Settles, Manager, Processor Cores Applications, LSI Logic Corporation

S225 400-MHz Frequency Counter Uses Low-Power Design Methods
Peter Alfke, Director Applications Engineering, Xilinx

H214 Differential Impedance Design and Verification with a Time Domain Reflectometry(TDR)
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Product Manager, Agilent

H224 Design Considerations for Gigabit Backplane Systems
Tom Cohen, New-Product Development, Teradyne
Gautam Patel, Signal-Integrity Engineer, Teradyne
Katie Rothstein, Signal-Integrity Engineer, New-Product Development, Teradyne

I214 Design Considerations for Low-Power Microprocessor Cores
Simon Segars, Group Leader, American Business System, ARM

I224 IP Modeling-Model Portability and Protection
Jefferry P. Vo, Engineering Manager, Research and Development, Synopsys

W215 Arial Case Study Mark McDiarmid, Director, Logica

W225 Using Video Standards for Eye-Opening Data Transmission: Megabits @ Many Meters xDSL
James Mears, Principal Engineer, National Semiconductor Corporation

Panel: Overcoming the Barriers in System-on-Chip Design
Mark D. Birnbaum, Director-Strategic Technology, World Wide Systems LSI Technologies, Fujitsu Microelectronics

H215 High-Speed Digital Interconnect Modeling from TDR Measurements
Dima Smolyansky, Product Marketing Engineer, TDA Systems
Steven Corey, Principal Engineer, TDA Systems

H225 Case Study: Signal-Integrity Problems and Solutions in the Simulation and Characterization of 1.5–3–Gbps Differential Backplane/Connector/ Daughter Card Transmission Systems
Paul Nikolich, Broadband Access Systems
Robert Sullivan, Vice President and Corporate Director-Technology, Hybricon
Joseph Plunkett, Simulation Engineer, Hybricon

I215 Embedded DRAM Application Tradeoffs Timothy Dell, Senior Applications Engineer, IBM Microelectronics

I225 30 Micro-Amp ADC Converter Using Asynchronous Control Logic for Low Power
Tracy Johancsik, IC Design Engineer, SliceX
Rex Hales, IC Design Engineer, SliceX

W313 Smartserver and Embedded Technologies for Wireless Integrated GPS
Norman Krasner, Vice President-Technology, Snaptrack
Len Sheynblat, Global Point System Architect, Snaptrack
W321 Design of the Knockout Switch Fabric with Behavioral Synthesis
Karim Khordac, Assistant Professor, McGill University
Daghan Altas, Customer Application Engineer, CoWare

S311 Next-Generation Concurrent Engineering for Complex Dual-Platform Subsystem Design
David A. Burgoon, Senior Productivity Engineer, Hewlett-Packard
Edward W. Powell, Productivity Engineer, Hewlett-Packard
Lief J. Sorensen, Member of Technical Staff, Hewlett-Packard
John Sundragon-Waitz, Senior Productivity Engineer, Hewlett-Packard

S321 Using Static Functional Verification in the Design of a Memory Controller
Sachi Sambandan, Program Manager, Cisco Systems
Mark Ross, Director of Engineering, Cisco Systems

H311 Integrated PLLs in PLDs
Joe DeLaere, Engineer-Applications, Altera Corporation

H321 A Baker’s Dozen of High-Speed Differential Backplane Design Tips
John Goldie, Applications Engineering Manager, National Semiconductor Jinhua Chen, Signal Integrity Engineer, North East Systems Associates

I311 CarteZian ™: ZiLOG’s New 32-bit Xtensa™–Based RISC/DSP Communications Engine
Daryl RuDusky, Vice President, Microprocessor Business Unit, Zilog
Stephen Chan, Director, Design Engineering, Zilog
Rey Archide, Technical Marketing Manger, Tensilica
David Frase, Zilog
Luis Larzabal, Director, Zilog

I321 Proven Mixed-Signal Subsystems Are Pivotal to Rapid SoC Development
Erlend Olson, Chief Technology Officer, Pivotal Technologies

W311 Challenges of Multiple Handset Communication Systems
Ron Fraser, Chief Technology Officer, Voyager Technologies

W322 A 0.25 um CMOS IC Integrating 8 Ports of Low Power DSP–Based Ethernet Transceivers Room
Sehat Sutardja, President and Chief Executive Officer, Marvell Semicondutor

S312 Overcoming Challenges and Obstacles to System-on-Chip Products
Sam Azimi, Project Manager, Marvell Semiconductor

S322 Improving Timing Predictions for a Million-Gate ASIC by Increasing the Accuracy of Wire Parasitic Extraction Jon Stahl, Senior Designer, Avici Systems

H312 Programmable Low-Jitter 800-MHz Phase-Locked Loop Using a Triplet Architecture Clocking and Timing at High Speeds
Marshall Soares, Staff Engineer, SliceX
Rex Hales, IC Designer and Project Manager, SliceX
Richard Rea, SliceX

H322 BusLVDS Expands Applications for Low-Voltage Differential Signaling (LVDS)
Stephen Kempainen, System Architect, National Semiconductor

I312 Design of MPEG–2 Function with Embedded ManArray Cores
Gerald G. Pechanek, Director of Architecture, Billions of Operations per Second (BOPS®)
Bruce Schulman, Vice President, Business Development, Billions of Operations per Second (BOPS®)
Charles Kurak, Software Engineer, Billions of Operations per Second (BOPS®)

I322 Migrating South: Easing the Flight to Deep Submicron Libraries
Anthony Waitz, Director of Engineering Development, Silicon Library Services Group, Synopsys
Neal Stansby, Senior Manager, Research and Development, Cadabra Design Automation

Panel: The 3G World War of Standards
Chris Isaac, Chief Executive Officer, Australian Telecommunications Cooperative Research Centre

S313 The Software Microprocessor
Alexander Klaiber, Member of the Technical Staff, Transmeta

H313 Reliable SPICE Models for Lossy-Coupled Transmission Lines
Helmut Katzier, Director of Engineering-Information and Communication Networks, Siemens AG

H323 High-Performance Signaling Techniques with LVDS and LVPECL Using Advanced FPGAs
Brian Von Herzen, President, Rapid Prototypes
Jon Brunetti, Analog Design, Rapid Prototypes

I313 A Processor SuperCore™ Approach to Designing Complex SoCs
Michael R. Betker, Engineering Manager, Lucent Technologies

I323 Overcoming Challenges in Process Conversion of Analog and Mixed-Signal Blocks
Rex Hales, IC Design Engineer, SliceX

W312 Wireless IP for Home Networking and Cordless Telephony
Yoram Soloman, President, Voyager Technologies
Ron Fraser, Chief Technical Officer, Voyager Technologies

W323 Applying Emulation for Verification of SoC Designs: Three Case Studies
Ray Turner, Senior Product Marketing Manager, Quickturn

S314 The MAJC™ Program
Marc Tremblay, Chief Architect, Sun Microsystems

H314 Practical Guidelines for Implementing 4.8 Gbps in Copper Today and the Roadmap to 9.6 Gbps
Brent Rothermel, Electronics Packaging Engineer, Tyco Electronics

H324 Signal Integrity Solutions for a High-Speed GTLP Backplane
Craig Klem, Staff Applications Engineer, Fairchild Semiconductor
Michael Baxter, Senior Signal Integrity Design Engineer, North East Systems Associates

I314 Developing Configurable IP for System-on-Chip
Bill Cordan, Vice President, SoC Services, PalmChip
Ashwin Rao, Design Engineer, PalmChip
Scott Knowlton, Technical Marketing Manager, Synopsys

I324 A Real "Softness" of Mixed Signal "Hard" Virtual Components
Jean-François Pollet, Product Line Manager, Dolphin Integration
Frederic Pollet, Dolphin Integration
Daniel Calloud, Dolphin Integration

W314 Modulation and Demodulation Techniques for FPGAs
Ray Andraka, President, Andraka Consulting Group

W324 The Digital Entertainment Box: What Is It and What's In It?
Jon Peddie, Editor-in-Chief, Jon Peddie Associates

S315 A Multi-platform, Mixed HDL, SOC Verification-Environment
Subhodip Ghosh, Principal Design Engineer, Intrinsix
Tom Guerena, Principal Design Engineer, Intrinsix
John Johl, Principal Consulting Engineer, Intrinsix
Michael Porter, Principal Design Engineer, Intrinsix
Frederick Tarverdians, Technical Manager, Intrinsix

S324 Exploiting Embedded Programmable Technology: Parts 1 and 2
Michael Ayukawa, Product Manager, Lucent Microelectronics, Lucent Technologies

H315 Characterization of High-Speed, Differential-Pair, Flex-Based Interconnects
Eric D. Jensen, Senior Project Engineer, Packard Hughes Interconnect
Mike Resso, Product Manager, Agilent
Aaron Edwards, Signal Integrity Engineer, Packard-Hughes Interconnect
William Crumly, Senior Staff Engineer, Packard-Hughes Interconnect
Laurie Taira-Griffin, Packard-Hughes Interconnect

H325 Effective Signal Integrity Analysis Using IBIS Models Syed B. Huq, Signal Integrity Engineer-ELB SI Packaging and Design, Cisco Systems

I315 Maximizing Intellectual Property Reuse for PCI
Mao T. Wang, Customer Engineer, Quick Logic
Brian Faith, Customer Engineer, QuickLogic

I325 The Top-Down Design Methodology Using a VHDL–AMS Simulator
Ken Ruan, Corporate Staff Engineer, Modeling Research and Development, Analogy

W315 Bit True Modeling of a QAM Modulator and Demodulator for Implementation of a DOCSIS Cable-Modem Transceiver
Vijay Kadamby, ASIC Consultant, Mentor Graphics Corporation

W325 Phototonic Design Automation: The Photonic Transmission Design Suite
Arthur Lowery, Chief Technology Officer, Virtual Photonics
Dirk Breuer, Director, Virtual Photonics
Rod Vance, Virtual Photonics
Don Hewitt, Virtual Photonics
P.Harshavardhana, Virtual Photonics
Stefan Georgi, Virtual Photonics
Olaf Langmann, Virtual Photonics
Igor Koltchanov, Virtual Photonics
Rudi Mooseburger, Virtual Photonics
Ronald Freund, Virtual Photonics
Andre Richter, Virtual Photonics

S316 Whole-Design Formal Verification of a 5-Million Gate Design by Equivalence Checking Is Possible with a Small Memory Footprint
Roger B. Hughes, Technical Marketing Engineer, Mentor Graphics

S325 Content-Addressable Memory (CAM) and Its Applications
Sherri Azgomi, Component Applications Engineer, Altera

H316 Evaluation of Maximum Usable Lengths for Cabled Copper Interconnects
Michael Fogg, Member of Technical Staff-Circuits and Design, AMP

H326 Signal Integrity: How to Measure It Correctly
Mike P. Li, Senior Scientist, Wavecrest
Jan Wilstrup, Corporate Consultant, Wavecrest

Panel: IP Business Models that Satisfy the Customer and the Investor
John Barr, Managing Director, EDA Research Analyst, Needham & Company

W316 Driving Backplane at 2.5 Gbps with ORCA FPGA with an Embedded 622MHz CDR Core
James H. Jian, Field Applications Engineer, Lucent Technologies

W326 Optical Backplanes—Fantasy or Reality
Scott Schaeffer, Systems Architect, AMP
Beth Murphy, Product Manager, AMP

S411 Transitioning an Internally Developed ASIC Test Bench to Specman e
Robert Quist, Member of Technical Staff, Hewlett-Packard

S421 Parallel Processing in FPGA Applicable to Content-Addressable Memories
Jean-Louis Brelet, Staff Product Applications Engineer, Xilinx

H411 Measuring MilliOhms and PicoHenrys in Power-Distribution Networks
Istvan Novak, Signal-Integrity Staff Engineer, Sun Microsystems

H421 Crosstalk for Printer Circuit-Board Designers
Lynne Green, Engineer-HyperLynx Division, PADS Software

I411 A Reconfigurable Datapath and Programmable Logic–Based System-on-Chip Architecture
Neal S. Stollon, Vice President, Marketing and Sales, Infinite Technology
Robert (Les) Veal, Project Manager, Infinite Technology

I421 IP Reuse: Fact and Fiction
James Lee, Principal Consulting Engineer, Intrinsix

W411 Interference Rejection by Means of Null-Space Transformations
John Minkoff, Member of Technical Staff, Network Wireless, Lucent Technologies

W421 System/Module Packaging-Related Issues: A Case Study of System-Level Thermal Management and Physical Management of Electrical Cable and Optical Fiber
Kevin Williams, Chief Technical Officer, Mayan Networks
Robert Sullivan, Vice President and Corporate Director, Hybricon Corporation
Joseph Plunkett, Simulation Engineer, Hybricon

S412 Design for Debug Rules Have Changed for System-on-Chip Design
Paul Huang, Chief Executive Officer and Founder, NOVAS Software
Alfred Chan, Vice President, Vweb
Scott Sandler, Director of Marketing, NOVAS Software

S422 Area-Optimization Techniques for FPGA Designs
Balasrinivasan Sivakumar, Senior Hardware Engineer, Wipro Limited
Shashidhar Shankara, Senior Hardware Engineer, Wipro Limited

H412 Nanosecond Discontinuity Impact on Hot-Swap
Timothy R. Minnick, Senior Systems-Interconnect Engineer, AMP Circuits and Design, AMP
Hank Herrman, Member of Technical Staff, AMP
Jack Kelley, Senior Electrical Design Engineer, Motorola

H422 System-Reliability Analysis Using Signal-Flow Graphs
Ken Farrier, Signal-Processing Engineer, Tadiran Microwave Networks

I412 The IP Ecosystem: An Infrastructure to Cultivate IP Leverage
Scott Runner, Director of IP Solutions, Conexant Systems
Venu Sanaka, Conexant Systems
Elaine Yu, Conexant Systems
Kat Hsu, Synchronicity

I422 Designing Reusable SDRAM Controller Core
Mark Balch, Senior Design Engineer, DiviCom

W412 Circuit Analysis and Design Considerations of Broadband Surge Immunity Compliances
Mark Hendricks, Design Engineer, Transtector

W422 Multilayer Module Technology—A Cornerstone Technology for Next-Generation Wireless and other Communications Applications
Gerald Kolbe, Manager, Murata Electronics N America

S413 Comprehensive SoC Verification Using Enhanced Vera
Amy Bonsall, Design Engineer, Hewlett-Packard
Won Rhee, Design Engineer, Hewlett-Packard
Beth Leonard, Design Engineer, Hewlett-Packard

S423 High Level Data Structures in Verification and Behavioral Models
Bradley Smith, Senior Engineer, Qualis Design
Bernard Delay, Principal Design Engineer, Qualis Design

H413 EMI and the Printed Circuit Board Fundamentals, Concepts, and Design Techniques
Mark I. Montrose, Principal Consultant, Montrose Compliance Services

H423 PCI-X Doubling the Speed of the PCI Bus
Dwight Riley, Server Architect, Compaq

I413 Fujitsu’s Revolutionary Web-Based Engineering (WBE) Design Environment
Harry Dole, Manager, Special Projects, Fujitsu
Paul Retlewski Sr., Strategic Marketing Manager, Fujitsu

I423 System(s)-on-a-Chip Design Considerations for High Performance Graphics
Joe Del Rio, Vice President Technical Marketing, Stellar Semiconductor

W413 Achieving Low Power Through High Performance
Kan Lu, President and Chief Executive Officer, 3DSP

W423 Effects of Physical Parameters on the Conducted EMI Emission General Technology
R. Parthasarathy, Hardware Specialist, Wipro Limited