Tuesday, February 1, 2000
Santa Clara Convention Center, Santa Clara, CA
In his keynote message, Ahmed Nawaz, Lucent vice president of integrated circuits, microelectronics group, suggested that the communications revolution presents the opportunity to meet the following demands:
- 5 million messages via the Internet every 5 minutes
- 500 million voice transmissions every hour
- 50,000 new users every 24 hours
- 630 new lines installed every week
- double the Internet traffic every 100 days
- continued improvements as a result of lower silicon cost and better battery technology and modular software
The members on the VSIA mixed signal panel sponsored by the VSI Alliance presented a vision for advancements in mixed-signal design. One of these is analog circuit synthesis. Dr. Dennis K. Buss, vice president silicon technology development, Texas Instruments, as a member of the system-on-chip panel, stated that in the year 2000 more semiconductor revenue is forecasted from application to communication products than from application to computing products. Dr. Buss called this a change from the PC Era to the Internet Era. Products for the Internet Era are DSP and analog technology–based. In addition, Dr. Buss identified the tremendous opportunity to improve design methods for mixed-signal, system-on-chip integration.
On Wednesday, DesignCon will focus primarily on analog/mixed-signal chip design. Such presentations, more than ever before, will be enhanced by exhibitors of analog centric design solutions in the exhibition hall, which opens at 12:30 pm on Wednesday. The exhibition hall closes at 6:30 pm, but attendees should be ready for late-hour discussions with their peers afterwards.
On Wednesday and Thursday, DesignCon will include many sessions on IP, SOC, and systems verification application of new solutions where the customers using new solutions speak!
The biggest problem with attending DesignCon on Tuesday, Wednesday, and Thursday is that one person will not be able to attend the many don’t-miss parallel sessions. Solution: bring your entire design team!
Monday, January 31, 2000
TecForum speakers provided in-depth education on how electronic engineers can solve design problems that keep system and chip designers awake at night. Some speakers offered basic training on new technologies that engineers must understand to develop products.
In those areas where legacy design methods are no longer meeting the challenges of complex and often high-performance product design, TecForum speakers provided attendees with new design methodologies and EDA and laboratory verification techniques that have been successfully applied by early adopters on real designs.
Cary Ussery, president and CEO of Improv Systems, presented revolutionary examples of system-on-chip design. The Improv new methodology is novel in that SOC design moves from hardware or co-hardware/software design to application software development that determines the hardware architecture. The hardware architecture is implemented with programmable and configurable platforms consisting of processors, peripherals, and memories. With the Improv method, configurable platforms provide designers with the ability to customize a platform to a specific, scalable application or application domain.
Application examples provided were a scalable DSP accelerator and a CODEC.
Designing and verifying high-performance systems for good signal integrity was the topic of two Monday TecForums at DesignCon. Overflowing sessions were led by Mark Grabois, MTS, Fujitsu Network Communication, and Jennie Grosslight and Mike Resso of Agilent Technologies. The speakers provided theory but quickly translated the theory to practical application.
On Monday, Mike Keating of Synopsys, Pierre Bricaud of Mentor Graphics, and Jean-Pierre Gueguen shared their belief that much has been learned on optimum IP reuse to lay the foundation for new efficiencies and management techniques.
One specific TecForum on Monday provided comprehensive education on the standards path to 3G wireless. Tanveer ul-Haq, MTS, Lucent Technologies, discussed the global complexities of the path to the IMT–2000 standard, offering technology enablers that he sees on the horizon.
According to Monday's speakers, chip-verification engineers have new choices for deep submicron design. They may choose from vectorless methods encompassing static timing analysis and formal verification from Synopsys, white box verification using semiformal techniques with checkers from 0-In Design Automation, or electrically correct design techniques from Sapphire Design Automation.
On Tuesday, DesignCon will build upon the high-speed busses and signal integrity TecForum education with papers by recognized experts from companies such as Fairchild Semiconductor, PLX Technology, AMCC, AMP, Bogatin Enterprises, Agilent Technologies, Teradyne, TDA Systems, and Hybricon.
At 8:30 am, Andrew Grace of Fairchild Semiconductor will lead a panel entitled High-Performance Backplane Design—Where is it Headed? He will be joined by Ed Sayre, president and CEO of North East Systems; Thomas Hawkins, president and founder Thomas Hawkins, signal and systems engineering; and William Spreen, product definition manager, Fairchild Semiconductor.
On Tuesday, Ed Petryk, director of engineering; Subbu Meiyappan, senior design engineer, Philips Semiconductor; and Lexra developers Elliot Mednick and Timothy Dell of IBM Microelectronics further explored IP reuse and verification topics. Simon Segars, manager of CPU Development, ARM, will speak on design considerations for low-power design, and Curtis Settles, manager process core applications, LSI logic, will speak on silicon development platforms simplify system design.